• Journal of Power Electronics
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• v.16 no.2
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• pp.447-454
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• 2016

A single-ended primary-inductor converter (SEPIC) features low input current ripple and output voltage up/down capability. However, the switching devices in a two-level SEPIC suffer from high voltage stresses and switching losses. To cope with this drawback, this study proposes a three-level SEPIC that uses a low voltage-rated switch and thus achieves better switching performance compared with the two-level SEPIC. The three-level SEPIC can reduce switch voltage stresses and switching losses. The converter operation and control method are described in this work. The experimental results for a 500 W prototype converter are also discussed. Experimental results show that unlike the two-level SEPIC, the three-level SEPIC achieves improved power efficiency with balanced capacitor voltages.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.646-649
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• 2002

In this paper, a low-voltage CMOS squarer and a four-quadrant analog multiplier are presented. It is based on a source-coupled pair and a scaled-floating voltage generator which are modified to work as a voltage squaring and a sum/difference circuits. The proposed squarer/multiplier have been simulated with HSPICE, where -3㏈ bandwidth of 10MHz is achieved. The power consumption is about 0.6㎽, from a ${\pm}$1.5V supply, and the total harmonic distortion is less than 0.7%, with a 1.2V peak-to-peak 1MHz input signal.

• Proceedings of the KIEE Conference
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• 1998.07f
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• pp.1931-1933
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• 1998

In this paper, single-phase PWM AC to AC converter that operates with unit power factor and sinusoidal input line currents is presented. The output voltage of this converter is able to be obtain step up voltage as well as step down voltage. because the converter applies to operating method of buck-boost converter. The control of this converter is performed with PI control method. By using this control method low lipples in the output current and the voltage as well as fast dynamic response are achieved.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.205-208
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• 2000

In this paper, a low voltage CMOS analog four-quadrant multiplier using two V-I converters is presented. The proposed V-I converter is composed of the series composite transistor and the low voltage composite transistor. The designed analog four-quadrant multiplier has simulated by HSPICE using 0.25$\mu\textrm{m}$ n-well CMOS process parameters with a 2V supply voltage. Simulation results show that the power dissipation is 1.55㎿, the cutoff frequency is 489MHz, and the THD can be 0.26％ at maximum differential input of 1V$\sub$p-p/.

• Proceedings of the KIPE Conference
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• 2001.12a
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• pp.89-92
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• 2001

In conventional three-phase rectifiers, it was necessary to use a transformer to obtain low output voltage. In this paper, we propose a characteristic experimental of three-phase diode rectifiers circuit that achieves low voltage by using a very simple circuit configuration that does not have a transformer and does not need any complex control. We also describe the operation principle of the proposed circuit, and der?ive a theoretical formula for its current waveform. On the basis these theoretical values with experimentally obtained input output current characteristics, current amplification factor, and output voltage characteristics, allowed us to confirm the soundness of our theoretical analyses.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.12
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• pp.2257-2261
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• 2007

A new CMOS transresistance amplifier for low-voltage analog integrated circuit design applications is presented. The proposed transresistance amplifier circuit based on common-source and negative feedback topology is compared with other recent reported transresistance amplifier. The proposed transresistance amplifier achieves high transresistance gain, gain-bandwidth with the same input/output impedance and the minimum supply voltage $2V_{DSAT}+V_T$. Hspice simulation using 1.8V TSMC $0.18{\mu}m$ CMOS technology was performed and achieved $59dB{\Omega}$ transresistance gain which is above the maximum about $18dB{\Omega}$ compared to transresistance gain of the reported circuit.

• ETRI Journal
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• v.29 no.1
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• pp.70-78
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• 2007

A new low-voltage CMOS interface circuit with digital output for piezo-resistive transducer is proposed. An input current sensing configuration is used to detect change in piezo-resistance due to applied pressure and to allow low-voltage circuit operation. A simple 1-bit first-order delta-sigma modulator is used to produce an output digital bitstream. The proposed interface circuit is realized in a 0.35 ${\mu}m$ CMOS technology and draws less than 200 ${\mu}A$ from a single 1.5 V power supply voltage. Simulation results show that the circuit can achieve an equivalent output resolution of 9.67 bits with less than 0.23% non-linearity error.

• Journal of Power Electronics
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• v.18 no.4
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• pp.955-964
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• 2018

In this paper, an active capacitor-diode-switch (CDS) snubber is proposed for L-type current-fed isolated DC-DC converters. The proposed CDS-clamped converter has a number of advantages. It can achieve wide range zero-voltage switching (ZVS) on two switches, a continuous input current with a low ripple, a reduction of one active switch and high efficiency. The operating principles, analysis and parameter design guideline are presented. A 300 W prototype is built to test the proposed converter. Simulation and experimental results are shown at 30 V input voltage and 400 V output voltage.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.6
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• pp.1064-1069
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• 2010

Active clamp forward converter provides zero voltage switching, low voltage stress and wide input voltage range. The design technique leads to getting a higher efficiency under high switching frequency and optimal operating range. It is designed for notebook computer adapter with free input voltage and 19.5V/120W output ratings. The efficiency is measured to more than 90%. One of the most important circuit parts is the filter inductor besides the transformer in active clamp forward converter. In this paper, the process of inductor design is listed optimally.

• Journal of Industrial Technology
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• v.32 no.A
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• pp.115-118
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• 2012

Recently, there are a lot of papers in order to replace the electrolytic capacitor into the film capacitor in output of PFC(Power Factor Correction). However, the film capacitor, which has capacitance of low values, causes a large ripple voltage in output of PFC. The LED drivers are connected series in the output of PFC and affected by the magnitude of voltage ripple. In this paper, we have compared the fixed frequency method with the variable frequency for the constant-current control and propose the control method to avoid the sub-harmonic oscillation in the variable input voltage. An 80W PFC, using film capacitors instead of electrolytic capacitors, and LED driver has been built and compared the fixed frequency control method with the variable frequency control method.