• 한국태양에너지학회:학술대회논문집
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• 2008.11a
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• pp.90-95
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• 2008

An SHGC(Solar Heat Gain Coefficient) is a determinant of total flux of solar radiation coming indoor and a critical factor in evaluating heating and cooling load. U-value represents heat loss while SHGC denominates heat gain. Recently, windows with high solar gain, mid solar gain or low solar gain are being produced with the development of Low-E coating technology. This study evaluated changes in energy consumption for heating and cooling according to changes in SHGC when using double-layered Low-E glass and triple layered Low-E glass in relation to double layered clear glass as base glass. An Office was chosen for the evaluation. For deriving optical properties of each window, WINDOW 5 by LBNL, an U.S. based company. and the results were analyzed to evaluate performance of heat and cooling energy on anannual basis using ESP-r, an energy interpretation program. Compared to the energy consumption of the double layered clear glass, the double layered Low-E glass with high solar gain consumed $69.5kWh/m^2,yr$, 9% more than the double layered clear glass in cooling energy. The one with mid solar gain consumed $63.1kWh/m^2,yr$, 1% less than the base glass while the one with low solar gain consumed $57.6kWh/m^2,yr$, 10% less than the base glass. When it comes to tripled layered glass, the ones with high solar showed 2% of increase respectively while the one with mid solar gain and low solar gain resulted 5% and 11% in decrease in energy consumption due to low acquisition of solar radiation. With respect to cooling energy. it was found that the lower the SHGC. the less energy consumption becomes.

• Journal of IKEEE
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• v.22 no.2
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• pp.408-412
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• 2018

In this paper, a 26GHz variable gain amplifier fabricated using a 40nm CMOS process is studied. In the case of an automobile radar using 79 GHz, it is advantageous in designing and driving to drive down to a low frequency band or to use a low frequency band before up conversion rather than designing and matching the entire circuit to 79 GHz in terms of frequency characteristics. In the case of a Phased Array System that uses time delay through TTD (True Time Delay) in practice, down conversion to a lower frequency is advantageous in realizing a real time delay and reducing errors. For a VGA (Variable Gain Amplifier) operating in the 26GHz frequency band that is 1/3 of the frequency of 79GHz, VDD : 1V, Bias 0.95V, S11 is designed to be <-9.8dB (Mea. High gain mode) and S22 < (Mea. high gain mode), Gain: 2.69dB (Mea. high gain mode), and P1dB: -15 dBm (Mea. high gain mode). In low gain mode, S11 is <-3.3dB (Mea. Low gain mode), S22 <-8.6dB (Mea. low gain mode), Gain: 0dB (Mea. low gain mode), P1dB: -21dBm (Mea. Low gain mode).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.6
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• pp.853-856
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• 2021

In this paper, a low noise amplifier having high gain and low noise by using input and inter stage matching circuits has been designed. A current-reused two-stage common-source topology is adopted, which can obtain high gain and low power consumption. Deterioration of noise characteristics according to the source inductive degeneration matching is compensated by adopting additional matching circuits. Moreover trade-offs among noise, gain, linearity, impedance matching, and power dissipation have been considered. In this design, 0.18-mm CMOS process is employed for the simulation. The simulated results show that the designed low noise amplifier can provide high power gain and low noise characteristics.

• Journal of IKEEE
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• v.14 no.4
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• pp.257-262
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• 2010

We design a CMOS front-end with wide variable gain and low power consumption for 5.25 GHz band. To obtain wide variable gain range, a p-type metal-oxide-semiconductor field-effect transistor (PMOS FET) in the low noise amplifier (LNA) section is connected in parallel. For a mixer, single balanced and folded structure is employed for low power consumption. Using this structure, the bias currents of the transconductance and switching stages in the mixer can be separated without using current bleeding path. The proposed front-end has a maximum gain of 33.2 dB with a variable gain range of 17 dB. The noise figure and third-order input intercept point (IIP3) are 4.8 dB and -8.5 dBm, respectively. For this operation, the proposed front-end consumes 7.1 mW at high gain mode, and 2.6 mW at low gain mode. The simulation results are performed using Cadence RF spectre with the Taiwan Semiconductor Manufacturing Company (TSMC) $0.18\;{\mu}m$ CMOS technology.)

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.8
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• pp.959-965
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• 2019

In this paper, we design a low noise amplifier to support ka-band satellite communication systems using 65-nm RFCMOS process. The proposed low noise amplifier is designed with high-gain mode and low-gain mode, and is designed to control the gain according to the magnitude of the input signal. In order to reduce the power consumption, the supply voltage of the entire circuit is limited to 1 V or less. We proposed the gain control circuit that consists of the inverter structure. The 3D EM simulator is used to reduce the size of the circuit. The size of the designed amplifier including pad is $0.33mm^2$. The fabricated amplifier has a -7 dB gain control range in 3 dB bandwidth and the reflection coefficient is less than -6 dB in high gain mode and less than -15 dB in low gain mode.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.12
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• pp.2257-2261
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• 2007

A new CMOS transresistance amplifier for low-voltage analog integrated circuit design applications is presented. The proposed transresistance amplifier circuit based on common-source and negative feedback topology is compared with other recent reported transresistance amplifier. The proposed transresistance amplifier achieves high transresistance gain, gain-bandwidth with the same input/output impedance and the minimum supply voltage $2V_{DSAT}+V_T$. Hspice simulation using 1.8V TSMC $0.18{\mu}m$ CMOS technology was performed and achieved $59dB{\Omega}$ transresistance gain which is above the maximum about $18dB{\Omega}$ compared to transresistance gain of the reported circuit.

• ETRI Journal
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• v.29 no.6
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• pp.785-793
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• 2007

In this paper, we present an integrated rail-to-rail fully differential operational transconductance amplifier (OTA) working at low-supply voltages (1.5 V) with reduced power consumption and showing high DC gain. An embedded adaptive biasing circuit makes it possible to obtain low stand-by power dissipation (lower than 0.17 mW in the rail-to-rail version), while the high DC gain (over 78 dB) is ensured by positive feedback. The circuit, fabricated in a standard CMOS integrated technology (AMS 0.35 ${\mu}m$), presents a 37 V/${\mu}s$ slew-rate for a capacitive load of 15 pF. Experimental results and high values of two quality factors, or figures of merit, show the validity of the proposed OTA, when compared with other OTA configurations.

• Journal of electromagnetic engineering and science
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• v.17 no.4
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• pp.202-207
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• 2017

This paper presents the performance of a planar, low-profile, and wide-gain-bandwidth leaky-wave slit antenna in different thickness values of high-permittivity gallium arsenide substrates at terahertz frequencies. The proposed antenna designs consisted of a periodic array of $5{\times}5$ metallic square patches and a planar feeding structure. The patch array was printed on the top side of the substrate, and the feeding structure, which is an open-ended leaky-wave slot line, was etched on the bottom side of the substrate. The antenna performed as a Fabry-Perot cavity antenna at high thickness levels ($H=160{\mu}m$ and $H=80{\mu}m$), thus exhibiting high gain but a narrow gain bandwidth. At low thickness levels ($H=40{\mu}m$ and $H=20{\mu}m$), it performed as a metasurface antenna and showed wide-gain-bandwidth characteristics with a low gain value. Aside from the advantage of achieving useful characteristics for different antennas by just changing the substrate thickness, the proposed antenna design exhibited a low profile, easy integration into circuit boards, and excellent low-cost mass production suitability.

• Journal of Satellite, Information and Communications
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• v.12 no.2
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• pp.83-88
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• 2017

In this paper, we propose a three-element CRPA array with improved low-elevation gain. The proposed antenna consists of a feed patch and a radiating patch, and the feed patch is connected by a coaxial cable. The radiating patch is electromagnetically coupled to the feed patch, which allows to improve the low-elevation gain of the antenna. To demonstrate the suitability of the proposed antenna, the antenna characteristics are measured in a full anechoic chamber. The resulting bore-sight gain is 2.8 dBic with an axial ratio of 2.7 dB, and the average gain at the low-elevation direction of $75^{\circ}$ is -1.4 dBic. The results verify that the proposed antenna is suitable for CRPA arrays with anti-jamming capability.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.318-330
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• 2013

This paper presents a high-linearity low-noise small-size programmable gain amplifier (PGA) based on a new low-noise low-distortion differential amplifier and a proposed reconfiguration technique. The proposed differential amplifier combines an inverter-based differential pair with an adaptive biasing circuit to reduce noise and distortion. The reconfiguration technique saves the chip size by half by utilizing the same differential pair for the input transconductance and load-stage, interchangeably. Fabricated in $0.18-{\mu}m$ CMOS, the proposed PGA shows a dB-linear control range of 21dB in 16 steps from -11 dB to 10 dB with a gain error of less than ${\pm}0.33$ dB, an IIP3 of 7.4~14.5 dBm, a P1dB of -7~1.2 dBm, a noise figure of 13dB, and a 3-dB bandwidth of 270MHz at the maximum gain, respectively. The PGA occupies a chip area of $0.04mm^2$ and consumes only 1.3 mA from the 1.8 V supply.