• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.205-208
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• 2001

According to the IMT-2000 specification of 3GPP(3rd Generation Partnership Project) and 3GPP2, Turbo codes is selected as a FEC(forward error correction) code for even higher reliable data communication. In 3GPP complied IMT-2000 system, channel coding under consideration is the selective use of convolutional coding and Turbo codes of 1/3 code rate with 4 constraint length. Suggesting a new path metric normalization method, we achieved a low complexity and high performance SOVA decoder for Turbo Codes, Further more, we analyze the decoding performance with respect to update depth and find out the optimal value of it by using computer simulation. Based on the simulation result, we designed a SOVA decoder using VHDL and implemented it into the Altera EPF10K100GC503FPGA.

• ETRI Journal
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• v.36 no.4
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• pp.682-685
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• 2014

In this letter, we propose an efficient near-optimal detection scheme (that makes use of a generalized sphere decoder (GSD)) for blind multi-user multiple-input multiple-output (MU-MIMO) systems. In practical MU-MIMO systems, a receiver suffers from interference because the precoding matrix, the result of the precoding technique used, is quantized with limited feedback and is thus imperfect. The proposed scheme can achieve near-optimal performance with low complexity by using a GSD to detect several additional interference signals. In addition, the proposed scheme is suitable for use in blind systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3A
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• pp.337-346
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• 2004

Punctured convolutional codes increase transmission efficiency without increasing hardware complexity. However, Viterbi decoder supporting punctured codes requires long decoding length and large survivor memory to achieve sifficiently low bit error rate (BER), when compared to the Viterbi decoder for a rate 1/2 convolutional code. This Paper presents novel architecture adopting a pipelined trace-forward unit reducing survivor memory requirements in the Viterbi decoder. The proposed survivor path architecture reduces the memory requirements by removing the initial decoding delay needed to perform trace-back operation and by accelerating the trace-forward process to identify the survivor path in the Viterbi decoder. Experimental results show that the area of survivor path unit has been reduced by 16％ compared to that of conventional hybrid survivor path unit.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.42-49
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• 2016

This paper proposes a low-complexity generator which finds the first two minimum values using bit-serial scheme. A low-complexity generator is an important part for low-area LDPC decoders based on the min-sum decoding algorithm because the hardware complexity of generators utilizes a significant portion of LDPC decoders. To reduce hardware complexity, bit-serial LDPC decoders has been studied. The generator of the existing bit-serial LDPC decoders can find only the first minimum value, and thus it leads to a BER performance degradation. The proposed generator using bit-serial scheme finds the first two minimum values. Hence, it can improve the BER performance. In addition, the area-time complexity of the proposed generator is lower than those of the existing generators finding the first two minima.

• Journal of Broadcast Engineering
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• v.16 no.4
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• pp.635-646
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• 2011

In distributed video coding, low complexity encoder can be realized by shifting encoder-side complex processes to decoder-side. However, not only motion estimation/compensation processes but also complex LDPC decoding process are imposed to the Wyner-Ziv decoder, therefore decoder-side complexity has been one important issue to improve. LDPC decoding process consists of numerous iterative decoding processes, therefore complexity increases as the number of iteration increases. This iterative LDPC decoding process accounts for more than 60% of whole WZ decoding complexity, therefore it can be said to be a main target for complexity reduction. Previously, HDA (Hard Decision Aided) method is introduced for fast LDPC decoding process. For currently received parity bits, HDA method certainly reduces the complexity of decoding process, however, LDPC decoding process is still performed even with insufficient amount of parity request which cannot lead to successful LDPC decoding. Therefore, we can further reduce complexity by avoiding the decoding process for insufficient parity bits. In this paper, therefore, a parity request estimation method is proposed using bit plane-wise correlation and temporal correlation. Joint usage of HDA method and the proposed method achieves about 72% of complexity reduction in LDPC decoding process, while rate distortion performance is degraded only by -0.0275 dB in BDPSNR.

• Journal of Electrical Engineering and Technology
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• v.12 no.3
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• pp.1262-1270
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• 2017

Among various decoding algorithms of low-density parity-check (LDPC) codes, the min-sum (MS) algorithm and its modified algorithms are widely adopted because of their computational simplicity compared to the sum-product (SP) algorithm with slight loss of decoding performance. In the MS algorithm, the magnitude of the output message from a check node (CN) processing unit is decided by either the smallest or the next smallest input message which are denoted as min1 and min2, respectively. It has been shown that multiplying a scaling factor to the output of CN message will improve the decoding performance. Further, Zhong et al. have shown that multiplying different scaling factors (called a 2-dimensional scaling) to min1 and min2 much increases the performance of the LDPC decoder. In this paper, the simplified 2-dimensional scaled (S2DS) MS algorithm is proposed. In the proposed algorithm, we figure out a pair of the most efficient scaling factors which multiplications can be replaced with combinations of addition and shift operations. Furthermore, one scaling operation is approximated by the difference between min1 and min2. The simulation results show that S2DS achieves the error correcting performance which is close to or outperforms the SP algorithm regardless of coding rates, and its computational complexity is the lowest comparing to modified versions of MS algorithms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.459-468
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• 2003

This paper proposes a novel low-cost and high-speed Reed-Solomon (RS) decoder based on a new degree computationless modified Euclid´s (DCME) algorithm. This architecture has quite low hardware complexity compared with conventional modified Euclid´s (ME) architectures, since it can remove completely the degree computation and comparison circuits. The architecture employing a systolic away requires only the latency of 2t clock cycles to solve the key equation without initial latency. In addition, the DCME architecture using 3t＋2 basic cells has regularity and scalability since it uses only one processing element. The RS decoder has been synthesized using the 0.25${\mu}{\textrm}{m}$. Faraday CMOS standard cell library and operates at 200MHz and its data rate suppots up to 1.6Gbps. For tile (255, 239, 8) RS code, the gate counts of the DCME architecture and the whole RS decoder excluding FIFO memory are only 21,760 and 42,213, respectively. The proposed RS decoder can reduce the total fate count at least 23% and the total latency at least 10% compared with conventional ME architectures.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.6
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• pp.1056-1063
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• 2008

This paper describes an efficient design of a multi-standard Viterbi decoder that supports multiple constraint lengths and code rates. The Viterbi decoder is parameterized for the code rates 1/2, 1/3 and constraint lengths 7,9, thus it has four operation nodes. In order to achieve low hardware complexity and low power, an efficient architecture based on hardware sharing techniques is devised. Also, the optimization of ACCS (Accumulate-Subtract) circuit for the one-point trace-back algorithm reduces its area by about 35% compared to the full parallel ACCS circuit. The parameterized Viterbi decoder core has 79,818 gates and 25,600 bits memory, and the estimated throughput is about 105 Mbps at 70 MHz clock frequency. Also, the simulation results for BER (Bit Error Rate) performance show that the Viterbi decoder has BER of $10^{-4}$ at $E_b/N_o$ of 3.6 dB when it operates with code rate 1/3 and constraints 7.

• Journal of Communications and Networks
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• v.18 no.2
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• pp.210-217
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• 2016

In this paper, we propose a low complexity multiple-input multiple-output (MIMO) detection algorithm with adaptive interference mitigation in downlink multiuser MIMO (DL MU-MIMO) systems with quantization error of the channel state information (CSI) feedback. In DL MU-MIMO systems using the imperfect precoding matrix caused by quantization error of the CSI feedback, the station receives the desired signal as well as the residual interference signal. Therefore, a complexMIMO detection algorithm with interference mitigation is required for mitigating the residual interference. To reduce the computational complexity, we propose a MIMO detection algorithm with adaptive interference mitigation. The proposed algorithm adaptively mitigates the residual interference by using the maximum likelihood detection (MLD) error criterion (MEC). We derive a theoretical MEC by using the MLD error condition and a practical MEC by approximating the theoretical MEC. In conclusion, the proposed algorithm adaptively performs interference mitigation when satisfying the practical MEC. Simulation results show that the proposed algorithm reduces the computational complexity and has the same performance, compared to the generalized sphere decoder, which always performs interference mitigation.

• Journal of Broadcast Engineering
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• v.17 no.1
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• pp.179-190
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• 2012

In Distributed Video Coding(DVC), a low complexity encoder can be realized by shifting complex processes of encoder such as motion estimation to decoder. Since not only motion estimation/compensation processes but also channel decoding process needs to be performed at DVC decoder, the complexity of a decoder is significantly increased in consequence. Therefore, various fast channel decoding methods are proposed for the most computationally complex part, which is the channel decoding process in DVC decoding. As the channel decoding process becomes faster using various methods, however, the complexity of the other processes are relatively highlighted. For instance, the complexity of side information generation process in the DVC decoder is relatively increased. In this paper, therefore, a fast method for the DVC decoding is proposed by using adaptive search range method in side information generation process. Experimental results show that the proposed method achieves time saving of about 63% in side information generation process, while its rate distortion performance is degraded only by about 0.17% in BDBR.