• Journal of Korean Society of Transportation
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• v.18 no.1
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• pp.47-59
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• 2000

The purpose of this study is to develop travel-time estimation model using neural networks and prediction model using neural networks and kalman-filtering technique. The data used in this study are travel speed collected from inductive loop vehicle detection systems(VDS) and travel time collected from the toll collection system (TCS) between Seoul and Osan toll Plaza on the Seoul-Pusan Expressway. Two models, one for travel-time estimation and the other for travel-time Prediction were developed. Application cases of each model were divided into two cases, so-called, a single-region and a multiple-region. because of the different characteristics of travel behavior shown on each region. For the evaluation of the travel time estimation and Prediction models, two Parameters. i.e. mode and mean were compared using five-minute interval data sets. The test results show that mode was superior to mean in representing the relationship between speed and travel time. It is, however shown that mean value gives better results in case of insufficient data. It should be noted that the estimation and the Prediction of travel times based on the VDS data have been improved by using neural networks, because the waiting time at exit toll gates can be included for the estimation of travel time based on the VDS data by considering differences between VDS and TCS travel time Patterns in the models. In conclusion, the results show that the developed models decrease estimation and prediction errors. As a result of comparing the developed model with the existing model using the observed data, the equality coefficients of the developed model was average 88% and the existing model was average 68%. Thus, the developed model was improved minimum 17% and maximum 23% rather then existing model .

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.681-689
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• 2010

We will demonstrate a novel topology for the feedforward amplifier. This amplifier does not use a delay element thus providing an efficiency enhancement and a size reduction by employing a distributed element negative group delay circuit. The insertion loss of the delay element in the conventional feedforward amplifier seriously degrades the efficiency. Usually, a high power co-axial cable or a delay line filter is utilized for a low loss, but the insertion loss, cost and size of the delay element still acts as a bottleneck. The proposed negative group delay circuit removes the necessity of the delay element required for a broadband signal suppression loop. With the fabricated 2-stage distributed element negative group delay circuit with -9 ns of total group delay, a 0.2 dB of insertion loss, and a 30 MHz of bandwidth for a wideband code division multiple access downlink band, the feedforward amplifier with the proposed topology experimentally achieved a 19.4 % power added efficiency and a -53.2 dBc adjacent channel leakage ratio with a 44 dBm average output power.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.87-95
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• 2013

In this paper, 2.5 Gb/s burst-mode clock and data recovery(CDR) is presented. Digital frequency calibration scheme is adopted to eliminate mismatch between the input data rate and the output frequency of the gated voltage controlled oscillator(GVCO) in the clock recovery circuitry. A jitter rejection scheme is also used to reduce jitter caused by input data. The proposed burst-mode CDR is designed using 0.11 ${\mu}m$ CMOS technology. Post-layout simulations show that peak-to-peak jitter of the recovered data is 14 ps with 0.1 UI input referred jitter, and maximum tolerance of consecutive identical digit(CID) is 2976 bits without input data jitter. The active area occupies 0.125 $mm^2$ without loop filter and the total power consumption is 94.5 mW.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.3 s.333
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• pp.25-32
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• 2005

In this papers, we first, therefore, designed VCO(voltage controlled oscillator) that is composed of the dielectric resonator and the varactor diode, and then designed and fabricated PLDRO(phase locked dielectric resonator oscillator) that is combined with the sampling phase detector and loop filter. The measured results of the fabricated PLDRO at 12.05 [GHz] show the output power is 13.54 [dBm], frequency tuning range approximately +/- 7.5 [MHz], and Power variation over the tuning range less than 0.2 [dB], respectively. The phase noise which effects on bits error rate in digital communication is obtained with -114.5 [dBc/Hz] at 100 [KHz] offset from carrier, and The second harmonic suppression is less than -41.49 [dBc]. These measured results are found to be more improved than those of VCO without adopting PLL, and the phase noise and power variation performance characteristics show the better performances than those of conventional PLL.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.19-24
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• 2007

With recent advancement of high-speed, multi-gigabit data transmission capabilities, serial links have been more widely adopted in industry than parallel links. Since the parallel link design forces its transmitter to transmit both the data and the clock to the receiver at the same time, it leads to hardware's intricacy during high-speed data transmission, large power consumption, and high cost. Meanwhile, the serial links allows the transmitter to transmit data only with no synchronized clock information. For the purpose, clock and data recovery circuit becomes a very crucial key block. In this paper, a 5.4Gbps half-rate bang-bang CDR is designed for the applications of high-speed graphic DRAM interface. The CDR consists of a half-rate bang-bang phase detector, a current-mirror charge-pump, a 2nd-order loop filter, and a 4-stage differential ring-type VCO. The PD automatically retimes and demultiplexes the data, generating two 2.7Gb/s sequences. The proposed circuit is realized in 66㎚ CMOS process. With input pseudo-random bit sequences (PRBS) of $2^{13}-1$, the post-layout simulations show 10psRMS clock jitter and $40ps_{p-p}$ retimed data jitter characteristics, and also the power dissipation of 80mW from a single 1.8V supply.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.43 no.10
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• pp.902-909
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• 2015

In this paper, monovision based relative navigation for a satellite proximity operation is studied. The chaser satellite only uses one camera sensor to observe the target satellite and conducts image tracking to obtain the target pose information. However, by using only mono-vision, it is hard to get the depth information which is related to the relative distance to the target. In order to resolve the well-known difficulty in computing the depth information with the use of a single camera, the active contour method is adopted for the image tracking process. The active contour method provides the size of target image, which can be utilized to indirectly calculate the relative distance between the chaser and the target. 3D virtual reality is used in order to model the space environment where two satellites make relative motion and produce the virtual camera images. The unscented Kalman filter is used for the chaser satellite to estimate the relative position of the target in the process of glideslope approaching. Closed-loop simulations are conducted to analyze the performance of the relative navigation with the active contour method.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.70-77
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• 2013

We suggest a low area and high efficiency switched-mode power supply (SMPS) with a pulse width modulation (PWM) generator based on a pseudo relaxation-oscillating technique. In the proposed circuit, the PWM duty ratio is determined by the voltage slope control of an internal capacitor according to amount of charging current in a PWM generator. Compared to conventional SMPSs, the proposed control method consists of a simple structure without the filter circuits needed for an analog-controlled SMPS or the digital compensator used by a digitally-controlled SMPS. The proposed circuit is able to operate at switching frequency of 1MHz~10MHz, as this frequency can be controlled from the selection of one of the internal capacitors in a PWM generator. The maximum current of the core circuit is 2.7 mA, and the total current of the entire circuit including output buffer driver is 15 mA at 10 MHz switching frequency. The proposed SMPS has a simulated maximum ripple voltage of 7mV. In this paper, to verify the operation of the proposed circuit, we performed simulation using Dongbu Hitek BCD $0.35{\mu}m$ technology and measured the proposed circuit.

• Proceedings of the KSR Conference
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• 2006.11b
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• pp.802-810
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• 2006

For a thorough train control, the precise train position detection is necessarily required. The widely used current way for train position detection is the one of using track circuits. The track circuit has a simple structure, and has a high level of reliability. However trains can be detected only on track circuits, which have to be installed on all ground sections, and much amount of cost for its installation and maintenance is needed. In addition, for the track circuit, only discontinuous position detection is possible because of the features of the closed circuit loop configuration. As the recent advances in telecommunication technologies and high-tech vehicle-based control equipments, for the train position detection, the method to detect positions directly from on trains is being studied. Vehicle-based position detection method is to estimate train positions, speed, timing data continuously, and to use them as the control information. In this paper, the features of GPS navigation and DR navigation are analyzed, and the navigation filters are designed by constructing vehicle-based train position detection method by combining GPS navigation and DR navigation for their complementary cooperation, and by using kalman filter. The position estimation performance of the proposed method is also confirmed by simulations.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.271-274
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• 2014

This paper proposes high-performance SAO(Sample Adaptive Offset) in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. SAO is a newly adopted technique belonging to the in-loop filter in HEVC. The proposed SAO encoder hardware architecture uses three-layered buffers to minimize memory access time and to simplify pixel processing and also uses only adder, subtractor, shift register and feed-back comparator to reduce area. Furthermore, the proposed architecture consists of pipelined pixel classification and applying SAO parameters, and also classifies four consecutive pixels into EO and BO concurrently. These result in the reduction of processing time and computation. The proposed SAO encoder architecture is designed by Verilog HDL, and implemented by 180k logic gates in TSMC $0.18{\mu}m$ process. At 110MHz, the proposed SAO encoder can support 4K Ultra HD video encoding at 30fps in real time.