• The Journal of Korean-Japanese National Studies
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• no.33
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• pp.67-111
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• 2017

This article aims to shed light on the wartime labor mobilization of prisoners on a large scale in/across colonial Korea and beyond during the late wartime period. More specifically, this article reveals the logic and mode of mobilization, and sorts out nationwide mobilization cases in colonial Korea. To this end, this article draws on documents and magazines published by the criminal administration of the Japanese Government-General of Korea, as well as the memoirs of prisoners and prison staff including prison administrators and prison chaplains. With the onset of the wartime system, the labor work in prisons centered on the production of military supplies. In 1943, the labor mobilization began to organize the National Protection Corps and dispatch them to remote workplaces. For example, at the requests of the military, prisoners were selected and sent to Hainan Island, while others were sent to military factories and mining fields in the northern part of the country. The authorities specified and adjusted the criteria for imprisonment based on education, physical strength, and other physical and mental conditions. Unconverted ideological offenders were excluded from the mobilization, and instead put under separate control. In preparation for mobilization, the prisoners trained in military drills, received Japanese language education, and underwent assimilation as imperial subjects through the preaching in prison. In order to induce prisoners to volunteer, a legislation system based on the shortening of the prison terms, including the parole system, was also promoted under the wartime system. As a result, prisoners were forced to work harder and faster even under the lowest of wages, poor food and poor housing conditions, and they also filled vacancies in managerial positions by serving as supervisory assistants. The reward system for them, however, did not function properly towards the end of the war, and the number of escapes and infectious outbreaks, as well as mortality rates rapidly increased under the harsh conditions.

• Journal of the Korea Society of Computer and Information
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• v.28 no.7
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• pp.85-93
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• 2023

Software birthmark refers to a unique feature inherent in software that can be extracted from program binaries even in the absence of the original source code of the program. Like human genetic information, the similarity between programs can be calculated numerically, so it can be used to determine whether software is stolen or copied. In this paper, we propose a new birthmark technique for Android applications developed using Unity. The source codes of Unity-based Android applications use C# language, and since the core logic of the program is included in the DLL module, it must be approached in a different way from normal Android applications. In this paper, a Unity birthmark extraction and comparison system was implemented, and reliability and resilience were evaluated. The use of the Unity birthmark technique proposed in this paper is expected to be effective in preventing illegal copy or code theft of the Unity-based Android applications.

• Journal of Korea Entertainment Industry Association
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• v.13 no.8
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• pp.199-207
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• 2019

One philosopher said that knowing the identity of one clump of grass on the roadside could reveal all the mysteries of the universe. If you know one, you can know two. If you know two, you can know three. If you know the form, you can know the whole. If you know the image(eidos), you can know the non-image, life, and death. But we are wandering in a dream because we don't know the one clump of grass, "One". For a long time I have been searching for a road to know "One". While studying of the process searching the truth, not only do we reveal logic development making One a language, but also we would like to provide the application of cultural contents applied to that One.

• Journal of IKEEE
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• v.27 no.4
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• pp.494-500
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• 2023

Image processing is currently used in various fields. Among them, autonomous vehicles, medical image processing, and robot control require fast image processing response speeds. To fulfill this requirement, hardware design for real-time processing is being actively researched. In addition to the size of the input image, the hardware processing speed is affected by the size of the inactive video periods that separate lines and frames in the image. In this paper, we design three different scaler structures based on the type of line memories, which is closely related to the inactive video periods. The structures are designed in hardware using the Verilog standard language, and synthesized into logic circuits in a field programmable gate array environment using Xilinx Vivado 2023.1. The synthesized results are used for frame rate analysis while comparing standard image sizes that can be processed in real time.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• 대한공업교육학회지
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• v.33 no.1
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• pp.149-168
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• 2008

The purpose of this study is to verify the effect of PSpice instruction on academic achievement in 'Combination logic circuit' unit of 'Digital Logic Circuit' in industrial high school. Three kinds of null hypotheses were formulated. Two classes of the third grade of C technical high school in Gyeong-buk were divided into experimental group and control group in order to verify null hypotheses. In the experimental design, 'Non-equivalent control group pretest-posttest' model was utilized. This experiment was conducted for six classes, the experimental group was applied to PSpice instruction method before the circuit traning while the control group was applied to traditional lecture oriented method before the circuit traning. Window SPSS 10.0 korean language version program was used for the data analysis and independent sample t-test was used to identify the average of each group. Significance level was set to .05 level. The results obtained in this study were as follows; First, PSpice instruction had not an effect on academic achievement according to a group type. However, these instruction had an effect on the following sub-domains; the psychomotor domain. Second, PSpice instruction had not an effect on academic achievement according to a studies level. However, these instruction for middle and low level students had an effect on the cognitive and psychomotor domain, and for middle level students had an effect on the affective domain. Third, PSpice instruction had not an effect on shortening of a training requirement. However, this instruction for low level students had an effect on shortening of a training requirement. The study results of simulation instruction was chiefly efficient in the psychomotor domain. We could know that simulation instruction is efficient as went to a low level students than an upper level students. Thus, We may make the study effectiveness in various instruction method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.55-62
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• 2005

In this paper, we propose an efficient symbol detection algorithm for space-frequency OFDM (SF-OFDM) transmit diversity scheme and present the implementation results of the SF-OFDM WLAN baseband processor with the proposed algorithm. When the number of sub-carriers in SF-OFDM scheme is small, the interference between adjacent sub-carriers may be generated. The proposed algorithm eliminates this interference in a parallel manner and obtains a considerable performance improvement over the conventional detection algorithm. The bit error rate (BER) performance of the proposed detection algorithm is evaluated by the simulation. In the case of 2 transmit and 2 receive antennas, at $BER=10^{-4}$ the proposed algorithm obtains about 3 dB gain over the conventional detection algorithm. The packet error rate (PER), link throughput, and coverage performance of the SF-OFDM WLAN with the proposed detection algorithm are also estimated. For the target throughput at $80\%$ of the peak data rate, the SF-OFDM WLAN achieves the average SNR gain of about 5.95 dB and the average coverage gain of 3.98 meter. The SF-OFDM WLAN baseband processor with the proposed algorithm was designed in a hardware description language and synthesized to gate-level circuits using 0.18um 1.8V CMOS standard cell library. With the division-free architecture, the total logic gate count for the processor is 945K. The real-time operation is verified and evaluated using a FPGA test system.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.3
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• pp.62-70
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• 2011

Nowadays image sensor is an essential component in many multimedia devices, and it is covered by a color filter array to filter out specific color components at each pixel. We need a certain algorithm to combine those color components reconstructed a full color image from incomplete color samples output from an image sensor, which is called a demosaicking process. Most existing demosaicking algorithms are developed for ideal image sensors, but they do not work well for the practical cases because of dissimilar characteristics of each sensor. In this paper, we propose a new demosaicking algorithm in which the color filter characteristics are fully utilized to generate a good image. To demonstrate significance of our algorithm, we used a commerically available sensor, CBN385B, which is a sort of Honeycomb-style CFA(Color Filter Array) CCD image sensor. As a performance metric of the algorithm, PSNR(Peak Signal to Noise Ratio) and RGB distribution of the output image are used. We first implemented our algorithm in C-language for simulation on various input images. As a result, we could obtain much enhanced images whose PSNR was improved by 4~8 dB compared to the commonly idealized approaches, and we also could remove the inclined red property which was an unique characteristics of the image sensor(CBN385B).Then we implemented it in hardware to overcome its problem of computational complexity which made it operate slow in software. The hardware was verified on Spartan-3E FPGA(Field Programable Gate Array) to give almost the same performance as software, but in much faster execution time. The total logic gate count is 45K, and it handles 25 image frmaes per second.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.61-68
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• 2008

In this paper, we propose an efficient hardware architecture and algorithm to increase an encoding process rate and implement a hardware for CABAC (Context Adaptive Binary Arithmetic Coding) which is used with one of the entropy coding ways for the latest video compression technique, H.264/AVC (Advanced Video Coding). CABAC typically provides a better high compression performance maximum 15% compared with CAVLC. However, the complexity of operation of CABAC is significantly higher than the CAVLC. Because of complicated data dependency during the encoding process, the complexity of operation is higher. Therefore, various architectures were proposed to reduce an amount of operation. However, they have still latency on account of complicated data dependency. The proposed architecture has two techniques to implement efficient pipeline architecture. The one is quick calculation of 7, 8th bits used to calculate a probability is the first step in Binary arithmetic coding. The other is one step reduced pipeline arcbitecture when the type of the encoded symbols is MPS. By adopting these two techniques, the required processing time was reduced about 27-29% compared with previous architectures. It is designed in a hardware description language and total logic gate count is 19K using 0.18um standard cell library.

• Journal of Advanced Navigation Technology
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• v.15 no.2
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• pp.213-220
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• 2011

In this paper, the channel preprocessor with an area-efficient architecture is proposed for the MIMO symbol detector which can support four transmit and receive antennas. The proposed channel preprocessor can shrink the channel dimension to reduce the hardware complexity of the MIMO symbol detector. Also, the proposed channel preprocessor is implemented with very low complexity by using QR decomposition (QRD) and log-number system (LNS). By applying QRD and LNS to the nulling matrix calculation block, the numbers of matrix-multiplications and matrix-divisions are decreased and thus the complexity of the proposed channel preprocessor is significantly reduced. The proposed channel preprocessor was designed in a hardware description language (HDL) and synthesized to gate-level circuits using 0.13um CMOS standard cell library. With the proposed channel preprocessor, the number of logic gates for channel preprocessor is reduced by 20.2% compared with the conventional architecture.