Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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Analysis of the Image Processing Speed by Line-Memory Type

라인메모리 유형에 따른 이미지 처리 속도의 분석

  • Si-Yeon Han (Dept. of Electronics Engineering, Dong-A University) ;
  • Semin Jung (Dept. of Electronics Engineering, Dong-A University) ;
  • Bongsoon Kang (Dept. of Electronics Engineering, Dong-A University)
  • Received : 2023.11.29
  • Accepted : 2023.12.18
  • Published : 2023.12.31
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Abstract

Image processing is currently used in various fields. Among them, autonomous vehicles, medical image processing, and robot control require fast image processing response speeds. To fulfill this requirement, hardware design for real-time processing is being actively researched. In addition to the size of the input image, the hardware processing speed is affected by the size of the inactive video periods that separate lines and frames in the image. In this paper, we design three different scaler structures based on the type of line memories, which is closely related to the inactive video periods. The structures are designed in hardware using the Verilog standard language, and synthesized into logic circuits in a field programmable gate array environment using Xilinx Vivado 2023.1. The synthesized results are used for frame rate analysis while comparing standard image sizes that can be processed in real time.

영상처리는 현재 다양한 분야에서 활용되고 있다. 그중 자율주행 자동차, 의료 영상처리, 로봇 제어 등은 빠른 영상처리 응답 속도가 필요하다. 이를 충족하기 위해 실시간 처리를 위한 하드웨어 설계가 활발히 연구되고 있다. 하드웨어 처리 속도는 입력 영상의 크기 외에도, 이미지에서 라인과 프레임을 구분하는 비활성화 영상 공백 구간의 크기에 영향을 받는다. 본 논문에서는 비활성화 영상 공백 구간과 밀접한 관련이 있는 라인메모리 유형에 따라 세 가지 스케일러 구조를 설계한다. 이 구조들은 Verilog 표준 언어를 사용하여 하드웨어로 설계되고, Xilinx Vivado 2023.1을 이용하여 field programmable gate array 환경에서 논리회로로 합성된다. 합성된 결과는 실시간 처리할 수 있는 표준 이미지 크기를 비교하면서 프레임 레이트 분석에 사용된다.

Keywords

Acknowledgement

This work was supported by the Ministry of Education of the Republic of Korea and the National Research Foundation of Korea(NRF-2023R1A2C1004592)

References

  1. Iuliana Chiuchisan, "A New FPGA-based Real-Time Configurable System for Medical Image Processing," 4th IEEE International Conference on E-Health and Bioengineering, 2013. DOI: 10.1109/EHB.2013.6707301
  2. K. Jack, Video Demystified: A Handbook for the Digital Engineer, 4th edition, Newnes, 2005.
  3. Ngo. D, S. Lee, U. J. Kang, T. M. Ngo, G. D. Lee, and B. Kang, "Adapting a Dehazing System to Haze Conditions by Piece-Wisely Linearizing a Depth Estimator," Sensors, vol.22, no.5, pp.1957-1981, 2022. DOI: 10.3390/s22051957
  4. T. M. Lehmann, C. Gonner, and K. Spitzer, "Survey: interpolation methods in medical image processing," IEEE Trans. Med. Imaging, vol.18, no.11, pp.1049-1075, 1999. DOI: 10.1109/42.816070
  5. H. M. Moon and S. B. Pan, "VLSI Architecture of Digital Image Scaler Combining Linear Interpolation and Cubic Convolution Interpolation," Journal of The Institute of Electronics and Information Engineers, vol.51, no.3, pp.112-118, 2014. DOI: 10.5573/ieie.2014.51.3.112
  6. Chips&Media, Method for scaling a resolution and an apparatus thereof. Korea Patent 10-1522261, 27, 2015, May 15, 2015.
  7. Xilinx, "Vivado Design Suite User Guide: Synthesis (UG901)," https://docs.xilinx.com/r/enUS/ug901-vivado-synthesis
  8. S. Y. Han, and B. Kang, "A Study of the Combinatorial Interpolation Algorithm for Scaler Hardware Design," Journal of IKEEE, vol.27, no.3, pp.296-302, 2023. https://doi.org/10.7471/IKEEE.2023.27.3.296
  9. IEEE Std 1364-2005 (Revision of IEEE Std 1374-2001), "IEEE Standard for Verilog Hardware Description Language," 2006. DOI: 10.1109/IEEESTD.2006.99495
  10. S. Jung, S. Y. Han, and B. Kang, "Design of a Variable-Mode Sync Generator for Implementing Digital Filters in Image Processing," Journal of IKEEE, vol.27, no.3, pp.273-279, 2023. https://doi.org/10.7471/IKEEE.2023.27.3.273