• Title/Summary/Keyword: logic gates

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Circuit Design of QAM Signal Mapper for Rotationally Invariant I/Q TCM (회전 불변 I/Q TCM을 위한 QAM 신호 사상기 회로 설계)

  • Kim, Chang-Joong;Lee, Ho-Kyoung
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.49 no.1
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    • pp.26-30
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    • 2012
  • In this paper, we propose a signal generation method of rectangular QAM for rotationally invariant I/Q TCM. The proposed method consists of only digital logic gates without look-up table so that we can implement the system compactly. Our scheme can be applied to every rectangular QAM with the level higher than 64.

Compact Design of the Advanced Encryption Standard Algorithm for IEEE 802.15.4 Devices

  • Song, Oh-Young;Kim, Ji-Ho
    • Journal of Electrical Engineering and Technology
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    • v.6 no.3
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    • pp.418-422
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    • 2011
  • For low-power sensor networks, a compact design of advanced encryption standard (AES) algorithm is needed. A very small AES core for ZigBee devices that accelerates computation in AES algorithms is proposed in this paper. The proposed AES core requires only one S-Box, which plays a major role in the optimization. It consumes less power than other block-wide and folded architectures because it uses fewer logic gates. The results show that the proposed design significantly decreases power dissipation; however, the resulting increased clock cycles for 128-bit block data processing are reasonable for IEEE 802.15.4 standard throughputs.

A NAND Flash Controller with Efficient Error Detection Unit (효율적인 오류검출 방식의 낸드 플래시 컨트롤러)

  • Baik, Chung-Taek;Lee, Yong-Hwan
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2007.10a
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    • pp.768-771
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    • 2007
  • Recently, Nand flash memory is widely used for digital equipments and its capacity and performance are rapidly improving. The limit on the number of writings and readings to/from Nand flash memory does not guarantee the integrity of its data. Therefore, ECC algorithm should be applied to the Nand flash controller. To reduce the access time, we use the look-up table to implement the ECC algorithm instead of the conventional logic gates.

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A study of microstructure of Ni-monosilicide fabricated with a thermal evaporator (열증착법으로 제조된 니켈 모노실리사이드의 미세구조 연구)

  • 안영숙;송오성;양철웅
    • Journal of the Korean institute of surface engineering
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    • v.32 no.6
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    • pp.703-708
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    • 1999
  • Silicides have been used extensively in ULSI logic device fabrication as contact materials for the active areas as well as the poly- Si gates. NiSi is a promising candidate for submicron device application due to less volume expansion, low formation temperature, little silicon consumption, and large stable processing temperature window. In this report, the microstructure of nickel silicides fabricated with a thermal evaporator has been investigated. We observed systematic transformation of Ni silicides of $Ni_2$Si, NiSi, $NiSi_2$, as annealing temperature increases. All the silicides have been identified by a X-ray diffractometer (XRD). The cross-sectional microstructure of silicides was examined by a transmission electron microscope (TEM) equipped with a energy dispersive spectrometer(EDS). The surface roughness of silicides was measured by scanning probe microscope(SPM). Although we observed thin oxide layer existed at the $Ni/NiSi_{x}$ interface, we fabricated successfully $550\AA$-thick planar Ni-monosilicide at the temperature range of$ 400~700^{\circ}C$.

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A VLSI Design for Digital Pre-distortion with Pipelined CORDIC Processors

  • Park, Jong Kang;Moon, Jun Young;Kim, Kyunghoon;Yang, Youngoo;Kim, Jong Tae
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.6
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    • pp.718-727
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    • 2014
  • In a wireless communications system, a predistorter is often used to compensate for the nonlinear distortions that result from operating a power amplifier near the saturation region, thereby improving system performance and increasing the spectral efficiency for the communication channels. This paper presents a new VLSI design for the polynomial digital predistorter (DPD). The proposed DPD uses a Coordinate Rotation Digital Computing (CORDIC) processor and a PD process with a fully-pipelined architecture. Due to its simple and regular structure, it can be a competitive design when compared to existing polynomial-type and approximated DPDs. Implementing a fifth-order distorter with the proposed design requires only 43,000 logic gates in a $0.35{\mu}m$ CMOS standard cell library.

The Effects of Types of Knowledge on the Performance of Fault Diagnosis (진단 수행도에 대한 지식형태의 효용에 관한 연구)

  • Ham, Dong-Han;Yoon, Wan-Chul
    • Journal of Korean Institute of Industrial Engineers
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    • v.22 no.3
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    • pp.399-412
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    • 1996
  • With respect to the effects of types of knowledge on human diagnostic performance, the results of several experiments claimed that training with procedural knowledge is more effective than training with principle knowledge. However, more useful results would be attained by investigating when and how the principles of system dynamics is valuable for diagnosis. Accordingly, we conducted an experiment to reevaluate the value of principle knowledge in two problem situations. A simulator system, named DLD, to diagnose an electronic device was created. It is a context-free digital logic circuit which includes forty-one gates of three basic types. The experiment investigated the effects of principle knowledge over common procedural knowledge. The experimental results showed that the effects of principle knowledge is dependent on the complexity of diagnostic situations. This adds up on experimental evidence against the presumed ineffectiveness of principle knowledge and forward reasoning in fault diagnosis. The results also suggest the source of the usefulness of principle knowledge.

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Sub-1.2-V 1-Gb Mobile DRAM with Ultra-low Leakage Current (극저 누설전류를 가지는 1.2V 모바일 DRAM)

  • Park, Sang-Kyun;Seo, Dong-Il;Jun, Young-Hyun;Kong, Bai-Sun
    • Proceedings of the IEEK Conference
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    • 2007.07a
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    • pp.433-434
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    • 2007
  • This paper describes a low-voltage dynamic random-access memory (DRAM) focusing on subthreshold leakage reduction during self-refresh (sleep) mode. By sharing a power switch, multiple iterative circuits such as row and column decoders have a significantly reduced subthreshold leakage current. To reduce the leakage current of complex logic gates, dual channel length scheme and input vector control method are used. Because all node voltages during the standby mode are deterministic, zigzag super-cutoff CMOS is used, allowing to Preserve internal data. MTCMOS technique Is also used in the circuits having no need to preserve internal data. Sub-1.2-V 1-Gb mobile DDR DRAM employing all these low-power techniques was designed in a 60 nm CMOS technology and achieved over 77% reduction of overall leakage current during the self-refresh mode.

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A Differential Current-to-Time Interval Converter Using Current-Tunable Schmitt Triggers

  • Chung, Won-Sup
    • Journal of IKEEE
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    • v.21 no.4
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    • pp.375-380
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    • 2017
  • A differential current-to-time interval converter is presented for current mode sensors. It consists of a ramp voltage generator, a current mode sensor, a reference current source, two current-tunable Schmitt triggers, a one-shot multivibrator, and two logic gates. The design principle is to apply a ramp voltage to each input of the two current-tunable Schmitt triggers whose threshold voltages are proportional to the drain current values of the current mode sensors. A proposed circuit converts a current change in the ISFET biosensor into its equivalent pulse width change. A prototype circuit built using TSMC 0.18 nm CMOS process exhibit a conversion sensitivity amounting to $726.9{\mu}s/pH$ over pH variation range of 2-12 and a linearity error less than ${\pm}0.05%$.

Control of Three-Phase Three-Switch Buck-Type Rectifier in EV Rapid Charging Systems

  • Chae, Beomseok;Suh, Yongsug
    • Proceedings of the KIPE Conference
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    • 2015.07a
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    • pp.189-190
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    • 2015
  • This paper investigates an economic and highly efficient power converter topology and its modulation scheme for 60kW rapid EV charger system. The target system consists of three-phase three-switch buck-type rectifier topology. A new Carrier Based PWM scheme along with its simple implementation using logic gates is introduced in this paper. This PWM scheme replaces the diode rectifier equivalent switching state with an active switching state producing the effectively same current flowing path. As a result, the distortion of input current during the polarity reversal of capacitor line voltage can be mitigated. The proposed modulation technique is confirmed through simulation verification. The proposed modulation technique and its implementation scheme can expand the operation range of the three-phase three-switch buck-type rectifier having ac input and capacitor ripple current of high quality.

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Molecular Computing with Artificial Neurons

  • Michael Conrad;Zauner, Klaus-Peter
    • Communications of the Korean Institute of Information Scientists and Engineers
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    • v.18 no.8
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    • pp.78-89
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    • 2000
  • Today's computers are built up from a minimal set of standard pattern recognition operations. Logic gates, such as NAND, are common examples. Biomolecular materials offer an alternative approach, both in terms of variety and context sensitivity. Enzymes, the basic switching elements in biological cells, are notable for their ability to discriminate specific molecules in a complex background and to do so in a manner that is sensitive to particular milieu features and indifferent to others, The enzyme, in effect, is a powerful context sensitivity pattern processor that in a rough way can be analogized to a neuron whose input-output behavior is controlled by enzymatic dynamics.

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