• JSTS:Journal of Semiconductor Technology and Science
• /
• 제17권1호
• /
• pp.65-78
• /
• 2017

Single Event Transient has a critical impact on highly integrated logic circuits which are currently common in various commercial and consumer electronic devices. Reliability against the soft and intermittent faults will become a key metric to evaluate such complex system on chip designs. Our previous work analyzing soft errors was focused on parallelizing and optimizing error propagation procedures for individual transient faults on logic and sequential cells. In this paper, we present a new propagation technique where a fault binary decision diagram (BDD) continues to merge every new fault generated from the subsequent logic gate traversal. BDD-based transient fault analysis has been known to provide the most accurate results that consider both electrical and logical properties for the given design. However, it suffers from a limitation in storing and handling BDDs that can be increased in size and operations by the exponential order. On the other hand, the proposed method requires only a visit to each logic gate traversal and unnecessary BDDs can be removed or reduced. This results in an approximately 20-200 fold speed increase while the existing parallelized procedure is only 3-4 times faster than the baseline algorithm.

• 한국정보통신학회논문지
• /
• 제14권9호
• /
• pp.2071-2077
• /
• 2010

본 논문에서는 이미지 센서와 외부의 구성요소 들과의 정합 모듈을 FPGA(Field Programmable Gate Array)를 사용하여 설계하였다. 일반적으로, 저준위 이미지의 데이터를 동기화하기 위하여 SRAM이 요구된다. 본문에서는 신호와 픽셀 단위의 크기를 가진 이미지 신호를 동기화하기 위하여 FPGA를 사용하여 인터페이스의 정합 모듈을 설계함을 목적으로 한다. 본 논문에서는 픽셀 단위로 구현함으로써 고화질의 이미지를 얻을 수 있다. 사용한 이미지 센서와 TFT-LCD의 동작 주파수는 각각 50MHz와 6.5MHz이다. 또한, 구현한 대부분의 제어부는 FPGA에 내장되어 있고 Altera사의 Quartus II 저작도구를 사용하였으며, 설계된 논리 게이트의 수는 33,216 개다.

• Current Optics and Photonics
• /
• 제3권6호
• /
• pp.531-540
• /
• 2019

Spectral Amplitude Coding Optical Code Division Multiple Access (SAC OCDMA) is an advanced technique in asynchronous environments. This paper proposes design and implementation of a novel quantum logic gate (QLG) code, with code construction algorithm generated without following any code mapping procedures for SAC system. The proposed code has a unitary matrices property with maximum overlap of one chip for various clients and no overlaps in spectra for the rest of the subscribers. Results indicate that a single algorithm produces the same length increment for codes with weight greater than two and follows the same signal to noise ratio (SNR) and bit error rate (BER) calculations for a higher number of users. This paper further examines the performance of a QLG code based SAC-OCDMA system with NAND and direct detection techniques. BER analysis was carried out for the proposed code and results were compared with existing MDW, RD and GMP codes. We demonstrate that the QLG code based system performs better in terms of cardinality, which is followed by improved BER. Numerical analysis reveals that for error free transmission (10^-9), the suggested code supports approximately 170 users with code weight 4. Our results also conclude that the proposed code provides improvement in the code construction, cross-correlation and minimization of noises.

• 센서학회지
• /
• 제29권1호
• /
• pp.68-73
• /
• 2020

This paper proposes an asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL) with advantages such as low area overhead, low power consumption compared with the conventional null convention logic (NCL) methodologies. The delay-insensitive NCL asynchronous circuits consist of dual-rail structures using {DATA0, DATA1, NULL} encoding which carry a significant area overhead by comparison with single-rail structures. The area overhead can lead to high power consumption. In this paper, the proposed single gate SCL deploys a power gating structure for a new {DATA, SLEEP} encoding to achieve low area overhead and low power consumption maintaining high performance during DATA cycle. In this paper, the proposed methodology has been evaluated by a liquid state machine (LSM) for pattern and digit recognition using FPGA and a 0.18 ㎛ CMOS technology with a supply voltage of 1.8 V. the LSM is a neural network (NN) algorithm similar to a spiking neural network (SNN). The experimental results show that the proposed SG-SCL LSM reduced power consumption by 10% compared to the conventional LSM.

• 한국산업정보학회논문지
• /
• 제19권6호
• /
• pp.1-6
• /
• 2014

지연 무관방식의 NCL 비동기 설계는 혁신적인 비동기 회로 설계 방식의 하나로써 견고성, 소비전력 그리고 용이한 설계의 재사용과 같은 많은 장접을 가지고 있다. 그러나, 기존의 NCL 게이트 셀들의 트랜지스터-레벨 구조들은 느린 스피드, 높은 영역 오버헤드, 높은 와이어(wire) 복잡도와 같은 약점 또한 가지고 있다. 따라서, 본 논문에서는 빠른 스피드, 낮은 영역 오버헤드, 낮은 와이더 복잡도를 위해서 트랜지스터 레벨에서 설계된 새로운 고속의 NCL 게이트 셀을 제안하고자 한다. 제안된 고속의 NCL 게이트 셀들은 회로 지연, 영역, 소모 전력에 의해서 기존의 다른 NCL 게이트 셀들과 비교되었다..

• Nuclear Engineering and Technology
• /
• 제48권5호
• /
• pp.1192-1205
• /
• 2016

Field programmable gate array (FPGA)-based systems are thought to be a practical option to replace certain obsolete instrumentation and control systems in nuclear power plants. An FPGA is a type of integrated circuit, which is programmed after being manufactured. FPGAs have some advantages over other electronic technologies, such as analog circuits, microprocessors, and Programmable Logic Controllers (PLCs), for nuclear instrumentation and control, and safety system applications. However, safety-related issues for FPGA-based systems remain to be verified. Owing to this, modeling FPGA-based systems for safety assessment has now become an important point of research. One potential methodology is the dynamic flowgraph methodology (DFM). It has been used for modeling software/hardware interactions in modern control systems. In this paper, FPGA logic was analyzed using DFM. Four aspects of FPGAs are investigated: the "IEEE 1164 standard," registers (D flip-flops), configurable logic blocks, and an FPGA-based signal compensator. The ModelSim simulations confirmed that DFM was able to accurately model those four FPGA properties, proving that DFM has the potential to be used in the modeling of FPGA-based systems. Furthermore, advantages of DFM over traditional reliability analysis methods and FPGA simulators are presented, along with a discussion of potential issues with using DFM for FPGA-based system modeling.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
• /
• pp.1577-1580
• /
• 1987

This paper proposes a gate and functional level logic simulator which can be run on XENIX O.S. The simulator has hierarchical structure including Hardware Description Language compiler, Waveform Description Language compiler, and Simulation Command Language compiler. The Hardware Description Language compiler generates data structure composed of gate structure, wire structure, condition structure, and event structure. Simulation algorithm is composed of selective trace and event-driven methods. To improve simulation speed, Cross Referenced Linked List Structure ia defined in building the data structure of circuits.

• 전자공학회논문지A
• /
• 제31A권2호
• /
• pp.125-134
• /
• 1994

This paper proposes a new top-down technology mapping algorithm for minimizing the chip area and the path delay time of lookup table-based field programmable gate array(FPGA). First, we present the decomposition and factoring algorithm using common subexpre ssion which minimizes the number of basic logic blocks and levels instead of the number of literals. Secondly, we propose a cube packing algorithm considering the decomposition of gates which exceed m-input lookup table. Previous approaches perform the cube packing and the gate decomposition independently, and it causes to increase the number of basic logic blocks. Lastly, the efficiency.

• 전자공학회논문지A
• /
• 제28A권1호
• /
• pp.74-84
• /
• 1991

This paper presents an algorithm for technology-dependent logic optimization and technology mapping, and describes a performance-driven logic synthesis system, SILOS, implemented based on the proposed algorithm. The system analyzes circuits and resynthesizes the critical sections such that generated circuit operates opertes within time constraints, using only gate types supported by library for direct implementation. Experimental results show that the system can be a viable tool in synthesizing high-performance logic circuits.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제2권1호
• /
• pp.70-81
• /
• 2002

This paper describes a new basic element which shows a synaptic operation for neural logic applications and shows function feasibility. A key device for the logic operation is the insulated-gate pn-junction device on SOI substrates. The basic element allows an interface quite compatible to that of conventional CMOS circuits and vMOS circuits.