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A New Basic Element for Neural Logic Functions and Capability in Circuit Applications  

Omura, Yasuhisa (Dept. of Electronics, Faculty of Engineering, Kansai University)
Publication Information
Abstract
This paper describes a new basic element which shows a synaptic operation for neural logic applications and shows function feasibility. A key device for the logic operation is the insulated-gate pn-junction device on SOI substrates. The basic element allows an interface quite compatible to that of conventional CMOS circuits and vMOS circuits.
Keywords
SOI; gated-pn junction; neural logic; synaptic operation;
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1 Y. Omura, 'Two-Dimensionally Confined Injection Phenomena at Low Temperatures in Sub-10-nm-Thick SOI Insulated-Gate p-n-Junction Devices,' IEEE Trans. on Electron Devices, 43(1996) 436-443   DOI   ScienceOn
2 T. Geszti, 'Physical Models of Neural Networks,' World Scientific, Chap. 2
3 M. Akazawa and Y. Amemiya, 'Eliciting the Potential Functions of Single-Electron Circuits,' IEICE Trans. Electron., E80-C(1997)849-858
4 Y. Sekine, M. Noguchi, T. Ito and M. Suyama, 'Pulse Type Hardware Neuron Model Using a Lamda (\Lambda)-Shaped Transistor and Its Application,' IEICE Trans. J69-D(1986)1343-1351
5 Y. Omura, 'Neuron Firing Operations by a New Basic Logic Element,' IEEE Electron Device Lett., 20(1999)226-228   DOI   ScienceOn
6 Y. Omura, 'A Lateral, Unidirectional, Bipolar-type Insulated-Gate Transistor - A Novel Semiconductor Device,' Appl. Phys. Lett., 40(1982)528-529   DOI
7 Y. Omura, 'A Lateral Unidirectional Bipolar-type Insulated-Gate Transistors - Operations, Characteristics and Applications,' Dig. of Tech. Papers, The 14th Conf. (1982 International) on Solid State Devices (Tokyo), 89-90
8 E. Tokumistu, R. Nakamura, and H. Ishiwara, 'Non-Volatile Metal-Ferroelectric-Insulator-Semiconductor (MFIS) FETs Using PLZT/STO/Si(100) Structures,' Ext. Abstract of the 1996 Int. Conf. on Solid State Devices and Materials (Yokohama), 845-847
9 J.-K. Shin, E. Io, K. Tsuji, H. Yonezu and N. Ohshima, 'A Novel Optical Adaptive Neuro-Device Using A Split-Gate MOS Transistor,' Ext. Abstract of the 1996 Int. Conf. on Solid State Devices and Materials (Yokohama), 848-850
10 T. Uemura and T. Baba, 'First Observation of Negative Differential Resistance in Surface Tunnel Transistors,' Jpn. J. Appl. Phys., 33 (1994) L207-L210   DOI   ScienceOn
11 Y. Omura, 'Negative Conductance Properties in Extremely Thin Silicon-on-Insulator (SOI) Insulated-Gate pn-Junction Devices (SOI Surface Tunnel Transistors),' Jpn. J. Appl. Phys., 35 (Pt.2) (1996) L1401-L1403   DOI   ScienceOn
12 T. Shibata and T. Ohmi, 'An Intelligent MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations, ' Tech. Dig. of IEEE 1991 Int. Electron Device Meetings,919-922   DOI
13 T. Akeyoshi, K. Maezawa and T. Mizutani, 'Weighted Sum Threshold Logic Operation of MOBILE (Monostable-Bistable Transition Logic Element) Using Resonant-Tunneling Transistors,' IEEE Electron Device Lett., 14 (1993) 475-477   DOI   ScienceOn
14 H. Ishii, T. Shibata, H. Kosaka and T. Ohmi, 'Hardware-Backpropagation Learning of Neuron MOS Neural Networks,' Tech. Dig. of IEEE 1992 Int. Eelectron Device Meetings, 435-438   DOI
15 D. R. Hush, W. D. Horne, 'Progress in Supervised Neural Networks - what's new since Lippman,' The IEEE Signal Processing Magazine, Jan. (1993)8-38   DOI   ScienceOn
16 D. Hammerstorm, 'Neural Networks at Works,' IEEE Spectrum, June (1993)26-32   DOI   ScienceOn