• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.4
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• pp.84-92
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• 2002

As today's field programmable gate arrays have very large logic capacity as well as relatively fast operation speed, they're widely used in many application areas. However, debugging the design implemented in FPGA's is very time-consuming and painful as the internal signal probing usually requires large number of FPGA re-compilations, which take tremendously long time. In this paper, we analyze the problems in FPGA debugging and propose a new powerful debugging solution. With the proposed FPGA debugging solution, we can guarantee not only to provide 100% internal signal visibility without FPGA re-compilation for the design in FPGA's, but also to identify at least one design bug per FPGA compilation. An experimental result has clearly shown the proposed approach to FPGA debugging very powerful and practical.

• Journal of Computing Science and Engineering
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• v.11 no.1
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• pp.9-23
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• 2017

NuDE 2.0 (Nuclear Development Environment 2.0) is a formal-method-based software development, verification and safety analysis environment for safety-critical digital I&Cs implemented with programmable logic controller (PLC) and field-programmable gate array (FPGA). It simultaneously develops PLC/FPGA software implementations from one requirement/design specification and also helps most of the development, verification, and safety analysis to be performed mechanically and in sequence. The NuDE 2.0 now consists of 25 CASE tools and also includes an in-depth solution for indirect commercial off-the-shelf (COTS) software dedication of new FPGA-based digital I&Cs. We expect that the NuDE 2.0 will be widely used as a means of diversifying software design/implementation and model-based software development methodology.

• Journal of Radiation Protection and Research
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• v.12 no.1
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• pp.12-25
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• 1987

A basic multichannel analyser (MCA) system have been designed and constructed with the successive approximation type ADC (Analog to Digital Converter). Linear Gate, window, and palse stretcher consist of mainly linear and logic IC's, and are properly combined together to achieve short dead time and good linearity of the system. ADC 1211 (analysing time: $120{\mu}sec$) and S-RAM (static random acess memory) 6264 are used in ADC module. Two 6264 memories are connected in parallel in order to-provide enough counting capacity ($2^{16}-1$). Interfaced microcomputer Apple II controls this system and analizes the counted data. The system is tested by input pulses between 0V to 10V from oscillator.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3A
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• pp.324-330
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• 2004

In this paper, we propose the TCM(Trellis coded modulation) decoding scheme that reduces the number of operations in branch metric with STBC(space time block codes) channel information and present the implementation results. The proposed TCM decoding scheme needs only 1 signal point in each TCM subset. Using bias point scheme, It detects the minimum distance symbol. The proposed TCM decoding scheme can reduce the branch metric calculations. In case of 16QAM 8 subset, the reduction ratio is about 50％ and for 64QAM 8 subset, about 80％ reduction can be obtained. The results of logic synthesis for the TCM and STBC decoder with the proposed scheme are 57.6K gate count.

• Journal of Magnetics
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• v.8 no.1
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• pp.24-31
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• 2003

The discoveries of antiferromagnetic coupling in Fe/Cr multilayers by Grunberg, the Giant Magneto Resistance by Fert and Grunberg and a large tunneling magnetoresistance at room temperature by Moodera have triggered enormous research on magnetic thin films and magnetoelectronic devices. Large opportunities are especially opened by the spin dependent tunneling resistance, where a strong dependence of the tunneling current on an external magnetic field can be found. We will briefly address important basic properties of these junctions like thermal, magnetic and dielectric stability and discuss scaling issues down to junction sizes below 0.01 $\mu\textrm{m}$$^2$with respect to single domain behavior, switching properties and edge coupling effects. The second part will give an overview on applications beyond the use of the tunneling elements as storage cells in MRAMs. This concerns mainly field programmable logic circuits, where we demonstrate the clocked operation of a programmed AND gate. The second 'unconventional' feature is the use as sensing elements in DNA or protein biochips, where molecules marked magnetically with commercial beads can be detected via the dipole stray field in a highly sensitive and relatively simple way.

• The Journal of the Korea Contents Association
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• v.6 no.11
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• pp.225-234
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• 2006

In this paper, we design a combined security processor, ECC, MD-5, and AES, as a SIP for cryptography of securing contents. Each SIP is modeled and designed in VHDL and implemented as a reusable macro through logic synthesis, simulation and FPGA verification. To communicate with an ARM9 core, we design a BFM(Bus Functional Model) according to AMBA AHB specification. The combined security SIP for a platform-based SoC is implemented by integrating ECC, AES and MD-5 using the design kit including the ARM9 RISC core, one million-gate FPGA. Finally, it is fabricated into a MPW chip using Magna chip $0.25{\mu}m(4.7mm{\times}4.7mm$) CMOS technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.419-426
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• 2014

This paper proposes a high-throughput encoding process and encoder architecture for quasi-cyclic low-density parity-check codes in IEEE 802.11ac standard. In order to achieve the high throughput with low complexity, a partially parallel processing based encoding process and encoder architecture are proposed. Forward and backward accumulations are performed in one clock cycle to increase the encoding throughput. A low complexity cyclic shifter is also proposed to minimize the hardware overhead of combinational logic in the encoder architecture. In IEEE 802.11ac systems, the proposed encoder is rate compatible to support various code rates and codeword block lengths. The proposed encoder is implemented with 130-nm CMOS technology. For (1944, 1620) irregular code, 7.7 Gbps throughput is achieved at 100 MHz clock frequency. The gate count of the proposed encoder core is about 96 K.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.391-394
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• 2006

The paper deals with the experimental GNSS receiver built at the Czech Technical University for experiments with the real GNSS signal. The receiver is based on software defined radio architecture. Receiver consists of the RF front end and a digital processor based on programmable logic. Receiver RF front end supports GPS L1, L2, L5, WAAS/EGNOS, GALILEO L1, E5A, E5B signals as well as GLONASS L1 and L2 signals. The digital processor is based on Field Programmable Gate Array (FPGA) which supports embedded processor. The receiver is used for various experiments with the GNSS signals like GPS L1/EGNOS receiver, GLONASS receiver and investigation of the EGNOS signal availability for a land mobile user. On the base of experimental GNSS receiver the GPS L1, L2, EGNOS receiver for railway application was designed. The experimental receiver is also used in GNSS monitoring station, which is independent monitoring facility providing also raw monitoring data of the GPS, EGNOS and Galileo systems via internet.

• 전기의세계
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• v.28 no.7
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• pp.49-55
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• 1979

This paper describes the mechanisms which breaks A.C. over-current protection in low voltage load. For the high speed over-current protection, it consists of thyristor switching circuit by forced commutation, IC logic gate controlled circuit and over-current detector with reed switch. Under various duty conditions, breacker was carried out several experiments and discussions. The results are as follows; (1) over-current cut off is possible within a quarter cycle (4ms at 60Hz) and clear is at least ten times faster than its electromechanical equivalent. (2) as the forced commutation thyristor circuit breaker has capability of high speed break, equivalent surgy current capacity of switching thyristor is increased more than twenty times of its rated current. (3) breaker using solid state dose not produce any harmful arc during switching period. Therefore the breaker above described may be considered an effective over-current protector for soli state power devices in industrial applications.

• The Transactions of the Korea Information Processing Society
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• v.4 no.11
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• pp.2923-2930
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• 1997

This paper describes two algorithms for technology mapping of multiple output functions into interesting and popular FPGAs (Field Programmable Gate Arrays) that lise look-up table memories. For improvement of technology mapping for FPGA, we use the functional decomposition method for multiple output functions. Two algorithms are proposed. The one is the Roth-Karp algorithm extended for multiple output functions. The other is the novel and efficient algorithm which looks for common decomposition functions through the decomposition procedure. The cost function is used to minimize the number of CLBs and nets and to improve performance of the network. Finally we compare our new algorithm with previous logic design technique. Experimental results show significant reduction in the number of CLBs and nets.