• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.509-510
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• 2006

FLL (Frequency Locked Loop) is the core block for high-speed transceiver. It incorporates a PLL for fine locking action, and a coarse controller for coarse locking action. A coarse controller compares frequencies coarsely and is applied to detected frequency difference directly. Compare to conventional FLL, frequency is applied to proposed FLL. Proposed FLL in this paper achieves only 5 cycles for coarse lock and total frequency locking time is 5 times faster than conventional FLL. Thus, proposed FLL is more useful to Ethernet transceiver application that requires high-speed data transfer than conventional FLL. Proposed FLL is based on $0.18{\mu}m$ process.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.246-248
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• 2007

This paper presents fast locking PLL(Phase Locked Loop) that can improve a jitter noise characteristics and acquisition process by designing a PFD(Phase Frequency Detector) circuit. The conventional PFD has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. The advanced PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, and it has excellent performances such as 1.75us of locking time and independent duty cycle characteristic. It is fabricated in a 0.018-${\mu}m$ CMOS process, and 1.8v supply voltage, and 25MHz of input oscillator frequency, and 800MHz of output frequency and is simulated by using ADE of Cadence.

• Proceedings of the KIEE Conference
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• 1999.11c
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• pp.742-744
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• 1999

In this paper, a new precharge type PFD for fast locking time of PLL is suggested. It is realized by inserting NMOS transistor and inverter into the precharge part of PFD for isolating the reset of the Up signal from the feedback signal. The new precharge type PFD generates the Up signal while the feedback signal is fixed at a high level. Therefore the new PFD output is increased than the conventional precharge type PFD output. As a result of the increased PFD output, fast locking of PLLs is achieved. Additionally, with control the falling time of the inverter, the dead-zone is reduced and the jitter characteristics are improved. The whole characteristics of PFD and PLL are simulated by using HSPICE. Simulation results show that the dead-zone is 20ps and the locking time of PLL using the new PFD is 38ns at the 350MHz frequency of referecne signal. This value is quite small compared with conventional PFD.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.1188-1191
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• 2003

In this paper, we focus our attention on the improvement of locking time and jitter parameter and propose the new structure of PLL which combined with the FVC, FOVI Matcher(FVC-Output and VCO-input Matching Circuit), Control Circuit and the conventional charge pump PLL. Using fast operation characteristics of the FVC, the circuit matching FVC-Output and VCO-input (FOVI Matcher) made to synchronize very fast. Fast locking time is usually required for application where the PLL has to settle rapidly if they switch from an idle mode to a normal mode and to track high-frequency data bit rate in data recovery systems. After a fast acqusition is achieved by the using the FVC, the conventional PLL operates for removing the phase error between the reference signal and the feedback signal. Therefore this structure can improve the trade-off between acquisition behavior and locked behavior.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.534-542
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• 2017

This paper presents a fast locking technique for a fractional-N PLL frequency synthesizer. The technique directly measures $K_{VCO}$ on a chip, computes the VCO's target tuning voltage for a given target frequency, and directly sets the loop filter voltage to the target voltage before the PLL begins the normal closed-loop locking process. The closed-loop lock time is significantly minimized because the initial frequency of the VCO are put very close to the desired final target value. The proposed technique is realized and designed for a 4.3-5.3 GHz fractional-N synthesizer in 65 nm CMOS and successfully verified through extensive simulations. The lock time is less than $12.8{\mu}s$ over the entire tuning range. Simulation verifications demonstrate that the proposed method is very effective in reducing the synthesizer lock time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.255-260
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• 2001

This paper describes the design of the Register Controlled DLL(Delay-Locked Loop) that achieves fast locking and low Power consumption using a new locking algorithm. A fashion for a fast locking speed is that controls the two controller in sequence. The up/down signal due to clock skew between a internal and a external clock in phase detector, first adjusts a large phase difference in coarse controller and then adjusts a small phase difference in fine controller. A way for a low power consumption is that only operates one controller at once. Moreover the proposed DLL shows better jitter performance Because using the lock indicator circuit. The proposed DLL circuit is operated from 50MHz to 200MHz by SPICE simulation. The estimated power dissipation is 15mA at 200MHz in 3.3V operation. The locking time is within 7 cycle at all of operating frequency.

• Journal of the Korea Furniture Society
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• v.20 no.2
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• pp.122-135
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• 2009

The objective of this work was to research click profile of laminate flooring by comparison of click and bonding laminate floorings, especially base on the click profile shape, bonding strength and international patents. Non-glue locking system has been used since laminate flooring was developed. For the reason of environment and saving installation time, the manufacturer in Europe and USA has developed click profile for laminate flooring. Each manufacturer has patent on each click profile. Although each click profile has good lock strength as shape, Berryand Unilin company's click profile systems showed higher locking strength than others. Korean laminate flooring company pay the fee of patent for using European and American manufacturer's click profile. From this work, we grope Korean style laminate flooring and click profile through research on the click profile shape, bonding strength and patents of European and American manufacturers.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.1891-1898
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• 1999

Traditional syntax-oriented serializability notions are considered to be not enough to handle in particular various types of transaction in terms of duration of execution. To deal with this situation, altruistic locking has attempted to reduce delay effect associated with lock release moment by use of the idea of donation. An improved form of altruism has also been deployed in extended altruistic locking in a way that scope of data to be early released is enlarged to include even data initially not intended to be donated. In this paper, we first of all investigated limitations inherent in both altruistic schemes from the perspective of alleviating starvation occasions for transactions in particular of short-lived nature. The idea of two-way donation locking(2DL) has then been experimented to see the effect of more than single donation in distributed database systems. Simulation experiments shows that 2DL outperforms the conventional two-phase locking in terms of the degree of oncurrency and average transaction waiting time.

• Clinics in Shoulder and Elbow
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• v.8 no.2
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• pp.117-121
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• 2005

A secure slip knot is very important in the arthroscopic surgery of the shoulder joint. The new 'Hallym Slider', developed by the first author(KCN), has the properties of being a simple sliding and one-way locking knot. This technique can be performed alone without an assistant and has no accidental premature locking during the knot tying. The initial slip knot determines the adequacy of tissue approximation and consequent healing. The 'Hallym Slider' has excellent initial holding capacity, maintaining tension on soft tissue while additional half-hitches are being tied. It locks readily, it takes less time to tie than numerous square knots, and it is not as bulky as other knots. Therefore, we introduce this new sliding and one-way locking knot during the arthroscpic surgery of shoulder.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.6
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• pp.58-64
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• 1997

The wavelengt lockin gsystem of the optical fabry-perot filter theoretially derived and experimentally realized by using the ithering method in order to compensate the laser wavelength drift increasing the BER of the WDM system. The deviation between the laser wavelength and the optical filter center wavelength is compensated by applying a suitable voltage to the PZT. Accordingly, the laser wavelength selected by the fabry-perot filter always maintains the condition of maximum transmission powr. A wavelength locking system has been demonstrated using a fiber fabry-perot filter with a free spectral range of 80nm and an FWH of 1nm. The voltages of the sine wave generated for dithering was 20mV and 10mV, the frequency was 2kHz and center wavelength of the tunable laser was 1550nm. In this paper, the locking system have 20ms of locking time and 2nm of locking range.