• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.582-586
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• 2005

This paper presents a new structure of Phase Locked Loop(PLL) which changes its loop bandwidth according to the locking status. The proposed PLL consists of a conventional PLL and, Locking Status Indicator(LSI). The LSI decides the operating bandwidth of loop filler. When the PLL becomes out of lock, the PLL increases the loop bandwidth and achieves fast locking. When the PLL becomes in-lock, this PLL decreases the loop bandwidth and minimizes phase noise output. The PLL can achieve fast locking and low phase noise output at the same time. Proposed PLL's locking time is less than $40{\mu}s$ and spur is 76.1dBc. It is simulated by HSPICE in a Hynix CMOS $0.35{\mu}m$ Process.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.607-608
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• 2008

Locking time of the DLL is the important design issue in case of clock gating for low power system. For precise analysis of the locking speed of the DLL, this paper analyzes the locking process of the DLL in time domain. Analysis result shows that the value of the DLL bandwidth over reference frequency should be limited to below 1 ($i.e.w_n/F_{REF}<1$) for the stable operation and relation between bandwidth and lock time is expressed by log function.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.963-966
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• 2003

This paper proposes a new locking algorithm of the delay locked loop (DLL) which reduces the lock-acquisition time and eliminates false locking problem to enlarge the operating frequency range. The proposed DLL uses the modified phase frequency detector (MPFD) and the modified charge pump (MCP) to avoid the false locking problem. Adopting a new lock detector that measures delay between elects helps the fast lock-acquisition time greatly. The idea has been confirmed by HSPICE simulations in a 0.35-${\mu}{\textrm}{m}$ CMOS process.

• Journal of information and communication convergence engineering
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• v.3 no.1
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• pp.18-22
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• 2005

This paper presents the analog adaptive phase-locked loop (PLL) architecture with a new adaptive bandwidth controller to reduce locking time and minimize jitter in PLL output for wireless communication. It adaptively controls the loop bandwidth according to the locking status. When the phase error is large, the PLL increases the loop bandwidth and reduces locking time. When the phase error is small, the PLL decreases the loop bandwidth and minimizes output jitters. The adaptive bandwidth control is implemented by controlling charge pump current depending on the locking status. A 1.28-GHz CMOS phase-locked loop with adaptive bandwidth control is designed with 0.35 $mu$m CMOS technology. It is simulated by HSPICE and achieves the primary reference sidebands at the output of the VCO are approximately -80dBc.

• Transactions on Semiconductor Engineering
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• v.2 no.4
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• pp.29-32
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• 2024

This Paper presents an analog charge-pump based phase-locked loop(PLL) for stabilizing the oscillation frequency of Ring Oscillator type Time-to-Digital Converter(TDC) in discrete Time-of-Flight Light detection and ranging(dToF LiDAR). To ensure the high resolution and accuracy of TDC, PLL is designed by stabilizing the oscillation frequency of TDC and reducing the phase noise. Even though the target time resolution of TDC is 200 ps, both PLL and TDC are designed with an operating frequency of 8.8 GHz due to variations in parasitic components after the process. The locking time of PLL is accomplished to stabilize the system with a fast locking time of PLL. The PLL is realized that locking time is less than 2.4 us, phase noise is -82.57 dBc/Hz at 1 MHz offset and the reference spur of 8.8 GHz is -46.24 dBc.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.3
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• pp.193-196
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• 2001

For wide locking range, an analog delay locked loop (DLL) was designed with the selective phase inversion scheme and the variable number of delay elements. The number of delay elements was determined adaptively depending on the clock cycle time. During the analog fine locking stage, a self-initializing 3-state phase detector was used to avoid the initial state problem associated with the conventional 3-state phase detector. With these schemes, the locking range of analog DLL was increased by four times compared to the conventional scheme according to the simulation results.

• Journal of KIISE:Databases
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• v.29 no.6
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• pp.464-476
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• 2002

Main-memory database systems which reside entire databases in main memory are suitable for high-performance real-time transaction processing. If two-phase locking(2PL) as concurrency control protocol is used for the transactions accessing main-memory databases, however, the possibility of lock conflict will be low but lock operations become relatively big overhead in total transaction processing time. In this paper, We designed a real-time static locking(RT-SL) protocol which minimizes lock operation overhead and reflects the priority of transactions and we implemented it on a main-memory real-time database system, Mr.RT. We also evaluate and compare its performance with the existing real-time locking protocols based on 2PL such as 2PL-PI and 2PL-HP. The extensive experiments reveal that our RT-SL outperforms the existing ones in most cases.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.275-278
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• 1999

In this paper, Dual PFD(Phase Frequency Detector) with improved phase locking time is proposed. The proposed PFD consists of positive and negative edge triggered D flip-flop. In order to confirm the characteristics of proposed PFD, HSPICE simulations are performed using a 0.25${\mu}{\textrm}{m}$ CMOS process. As a result of simulations, the proposed PFD has a characteristic of fast phase locking time with dead zone free.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.691-693
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• 2017

A novel structure of fast locking phase locked loop (PLL) with time difference detector and Lock status indicator (LSI) is proposed in this paper. Fast locking time is achieved using LSI. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.

• Journal of Korean Foot and Ankle Society
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• v.17 no.1
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• pp.45-51
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• 2013

Purpose: The purpose of this study was to compare and analyze the results of midfoot arthrodesis with locking plate fixation and the other instruments. Materials and Methods: Twenty one patients, a total of 22 feet who underwent midfoot arthrodesis at our institution were reviewed retrospectively from January 2006 to December 2011. Locking plates were used in 9 cases, and the other instruments such as K-wires, screws, staples were used in 13 cases. Radiologic union time was evaluated and compared between both groups. Preoperative & postoperative AOFAS midfoot scores were evaluated and compared as clinical results. Results: The average AOFAS score was rising from 69.7 to 89.4 in locking plate group and from 67.6 to 80.7 in the other instrument group. There was no statistically significant difference in two groups (p=0.179). The mean radiologic union time was 10.2 weeks in locking plate group, 12.6 weeks in the other instrument group with no significant difference (p=0.062). One case of peroneal nerve irritation was detected as a complication in locking plate group. One case of peroneal nerve irritation and 1 case of superficial wound infection with skin sloughing were detected in the other instrument group. Conclusion: There was no statistically significant difference for union time and clinical results in both groups. A locking plate can be one of the useful option for midfoot arthrodesis.