• 한국정보통신학회논문지
• /
• 제9권3호
• /
• pp.582-586
• /
• 2005

본 논문은 locking 상태에 따라서 루프대역폭이 변화하는 Phase Locked Loop (PLL)의 구조를 제안하였다. 제안한 PLL은 기본적인 PLL 블록과 NOR Gate, Inverter, Capacitor, 그리고 Schmitt trigger로 이루어진 Locking Status Indicator(LSI) 블록으로 구성되었다. LSI는 Loop Fille.(LF)에 공급되는 전류와 저항 값을 locking 상태에 따라 변화시켜서 unlock이 되면 넓은 루프대역폭 가지는 PLL로, lock이 되면 좁은 루프대역폭을 가지는 PLL로 동작하도록 한다. 이러한 구조의 PLL은 짧은 locking 시간과 저 잡음의 특성을 동시에 만족시킬 수 있다. 제안된 PLL은 Hynix CMOS $0.35{\mu}m$ 공정으로 Hspice 시뮬레이션 하였으며 40us의 짧은 locking 시간과 -76.1dBc 크기의 spur를 가진다.

• 한국유체기계학회 논문집
• /
• 제10권5호
• /
• pp.20-26
• /
• 2007

Some gate valves are susceptible to pressure locking and thermal binding which prevent the safety function. The safety related gate valves susceptible to pressure locking and thermal binding shall be identified and taken preventive actions to ensure the safety function. The identification of the gate valves susceptible to pressure locking and thermal binding needs the evaluation of system design, valve and piping arrangement, test requirements, and operating conditions. Application of preventive methods should consider the system safety function, applicability, effectiveness, interface with system design, and cost. The selection procedure of valves susceptible to pressure locking and thermal binding can be effectively used in industry including nuclear power plants. In order to prevent the pressure locking, the hole can be drilled through the one disc of upstream side or down stream and the external equalizing line can be installed from bonnet to downstream or upstream. The double disc parallel seat valve type can be used instead of flexible wedge gate valve to prevent the thermal binding. The identification of gate valves susceptible to pressure locking and thermal binding, and preventive actions will meet the regulatory requirements and enhance the availability and safety of plants.

• 한국공작기계학회논문집
• /
• 제15권6호
• /
• pp.121-126
• /
• 2006

Snap-fit is being used in manufacture of plastic products. Integral features using snap-fit are classified as locks, locators and enhancements. Locking features complete the process of attachment by providing physical interference to prevent separation. Looking feature pairs consist of two components, i.e., a flexible latch and a rigid catch and require particular care and attention for their selection. We can make several locking feature pairs by selecting latch and catch, but some parts restrict freedom of selection. Therefore, part designers must know the characteristic properties of generic locking feature forms as considering a specific design problem. In this paper, it has been presented about problem of small size products using locking feature and then introduced new locking feature applicable to small parts.

• Structural Engineering and Mechanics
• /
• 제37권6호
• /
• pp.633-648
• /
• 2011

This paper investigates the aspect-ratio locking of the isoparametric 8-node quadrilateral (QUAD8) element. An important finding is that, if finite element solution is carried out with in exact arithmetic (i.e., with no truncation and round off errors), the locking tendency of the element is completely avoided even for aspect-ratios as high as 100000. The current finite element codes mostly use floating point arithmetic. Thus, they can only avoid this locking for aspect-ratios up to 100 or 1000. A novel method is proposed in the paper to avoid aspect-ratio locking in floating point computations. In this method, the offending terms of the strain-displacement matrix (i.e., $\mathbf{B}$-matrix) are multiplied by suitable scaling factors to avoid ill-conditioning of stiffness matrix. Numerical examples are presented to demonstrate the efficacy of the method. The examples reveal that aspect-ratio locking is avoided even for aspect-ratios as high as 100000.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
• /
• pp.95-99
• /
• 2000

New locking algorithm of DLL is proposed to improve the locking speed and low power dissipation in this paper, In spite of using the architecture of delay controller, low power consumption is acquired by operating only one controller at once and fast locking speed is accomplished by initial setting from the coarse controller. The proposed DLL circuit is operated from 50MHz to 200MHz and locked within 6 cycle at all of operating frequency.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제1권3호
• /
• pp.193-196
• /
• 2001

For wide locking range, an analog delay locked loop (DLL) was designed with the selective phase inversion scheme and the variable number of delay elements. The number of delay elements was determined adaptively depending on the clock cycle time. During the analog fine locking stage, a self-initializing 3-state phase detector was used to avoid the initial state problem associated with the conventional 3-state phase detector. With these schemes, the locking range of analog DLL was increased by four times compared to the conventional scheme according to the simulation results.

• 한국전산구조공학회:학술대회논문집
• /
• 한국전산구조공학회 1993년도 봄 학술발표회논문집
• /
• pp.11-18
• /
• 1993

An Analytical study of shear locking is introduced for linear thick beam element. The appropriate sampling point which eliminate shear locking phenomenon was Proposed through this study. Reduced integration point is exactly same as the sampling point obtained from this study. Numerical example indicates how shear locking is serious. some solutions for shear locking are presented.

• Clinics in Shoulder and Elbow
• /
• 제17권4호
• /
• pp.159-165
• /
• 2014

Background: Kirschner's wire (K-wire) transfixation and locking hook plate fixation techniques are widely used in the treatment of acute acromioclavicular joint (ACJ) dislocation. The purpose of this study was to compare the clinical and radiologic outcomes between K-wires transfixation and a locking hook plate fixation technique. Methods: Seventy-seven patients with acute ACJ dislocation managed with K-wire (56 shoulders) and locking hook plate (21 shoulders) were enrolled for this study. The mean follow-up period was 61 months. Results: At the last follow-up, the shoulder rating scale of the University of California at Los Angeles (UCLA) was higher in patients treated with locking hook plate than with K-wires ($33.2{\pm}2.7$ vs. $31.3{\pm}3.4$, p=0.009). In radiologic assessments, coracoclavicular distance (CCD) (7.9 mm vs. 7.7 mm, p=0.269) and acromioclavicular distance (ACD) (3.0 mm vs. 1.9 mm, p=0.082) were not statistically different from contralateral unaffected shoulder in locking hook plate fixation group, but acromioclavicular interval (ACI) was significant difference. However, there were significant differences in ACI, CCD, and ACD in K-wire fixation group (p<0.001). Eleven complications (20%) occurred in K-wire transfixation group and 2 subacromial erosions on computed tomography scan occurred in locking hook plate fixation group. Conclusions: ACJ stabilization was achieved in acute ACJ dislocations treated with K-wires or locking hook plates. Locking hook plate can provide higher UCLA shoulder score than K-wire and maintain CCD, and ACD without ligament reconstruction. K-wire transfixation technique resulted in a higher complication rate than locking hook plate.

• 인터넷정보학회논문지
• /
• 제15권1호
• /
• pp.63-71
• /
• 2014

인공지능과 웹 데이터베이스와 같은 분야에서는 기존의 관계 데이터 모형보다 더 고급 모델링 기능을 필요로 한다. 이러한 분야에서 객체지향데이터베이스는 객체를 모아 클래스를 제공하고 또한 클래스 사이에서 상위클래스는 하위 클래스에게 물려주는 계층구조를 제공하기 때문에 더 좋은 데이터 모형이 될 수 있다. 본 논문의 목적은 객체지향데이터베이스에서 다중 계승을 위한 동시성 제어 기법을 개발하는 것이다. 본 논문에서 제안하는 MIIL(Multiple Inheritance Implicit Locking) 기법은 기존의 Implicit 로킹(Locking) 기법에 기반을 두었다. MIIL 기법은 기존의Implicit 로킹에서 불필요한 로킹을 제거하였다. 또한 본 논문에서 제안하는 MIIL 기법에서의 Intention 로킹은 기존의 Implicit 로킹기법과 동일하게 작동한다. 본 논문에서 제안한 MIIL 기법은 기존의 Implicit 로킹 기법보다 로킹 오버헤드가 적음을 증명하였다. 또한, 본 논문에서는 단일 계승과 다중 계승 등 계승구조만을 이용함으로써 로킹 오버헤드를 줄이기 위한 추가적인 비용을 필요로 하지 않는다.

• 한국통신학회논문지
• /
• 제26권12C호
• /
• pp.255-260
• /
• 2001

본 논문에서는 새로운 locking 알고리즘을 사용하여 저전력의 특정을 가지면서 locking 속도가 빠른 Register Controlled DLL(Delay-Locked Loop)을 설계하였다. Locking 속도의 향상을 위해 제안한 알고리즘은 coarse와 fine controller를 각각 동작시키는 것으로, phase detector에서 출력되는 up/down 신호를 먼저 coarse controller에 인가하여 외부 클럭과 내부 클럭의 큰 위상차를 줄이고, coarse controller를 고정시킨 상태에서 up/down 신호를 fine controller에 인가하여 미세 지연 시간을 조정하도록 하는 것이다. 또한 제안한 DLL은 dual controller를 사용하지만 locking 동작시 한 개의 controller만 동작하므로 소비 전력을 줄일 수 있었으며 lock indicator를 사용하여 좋은 지터 특성을 보였다. 제안한 DLL은 0.6 $\mu\textrm{m}$ CMOS 공정 파라메타를 이용하여 설계하였고, SPICE 모의실험결과 50 MHz에서 200MHz가지 동작하였다. 200MHz 동작시 소비되는 전류는 15mA이며 모든 주파수에서 7 주기 이내에 locking 되었다.