• 조명전기설비학회논문지
• /
• 제25권4호
• /
• pp.57-64
• /
• 2011

Most of the user has been used linear load and non-linear load. The former is usually inductive load which is needed power factor compensation, the latter is power conversion system device. Actually two kinds of load is used together in the customer application. Generally capacitor is used for power-factor compensation of inductive load and reduction harmonics of non linear load with reactor. Non-linear load generates harmonic current for its energy conversion process. If harmonic current pass along the low impedance side of distribution system, the magnification of voltage and current is appeared by the series and parallel resonance. As a result, condenser has received a bitter electrical stress by the harmonic component. In this paper, we analyzed that how resonance is changed by the 5-th harmonic current pattern and proposed an alternative plan for non-magnification.

• Journal of Power Electronics
• /
• 제16권3호
• /
• pp.1046-1055
• /
• 2016

A controller to mitigate the destabilizing effect of constant power load (CPL) is proposed for a DC/DC buck-boost converter. The load profile has been considered to be predominantly of CPL type. The negative incremental resistance of the CPL tends to destabilize the feeder system, which may be an input filter or another DC/DC converter. The proposed sliding mode controller aims to ensure system stability under the dominance of CPL. The effectiveness of the controller has been validated through real-time simulation studies and experiments under various operating conditions. The controller has been demonstrated to be robust with respect to variations in supply voltage and load and capable of mitigating instabilities induced by CPL. Furthermore, the controller has been validated using all possible load profiles, which may arise in modern-day DC-distributed power systems.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2002년도 하계학술대회 논문집 C
• /
• pp.1850-1852
• /
• 2002

In this paper, we studies EMTP analysis and characteristics of critical voltage of pulse corona and load impedance on variable electrode length. To obtain a stable Pulse voltage, we designed a compact pulse generator switched MOSFET and tested their characteristics by adjusting electrode length and pulse repetition. As a result, critical voltage of pulse corona and load impedance on increasing electrode length were decreased. These results indicate we can control critical voltage of pulse corona and suppress arc discharging between two electrodes.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2002년도 춘계합동학술대회 논문집
• /
• pp.184-186
• /
• 2002

In this paper, we studies EMTP analysis and characteristics of critical voltage of pulse corona and load impedance on variable electrode length. To obtain a stable pulse voltage, we designed a compact pulse generator switched MOSFET and tested their characteristics by adjusting electrode length and pulse repetition. As a result, critical voltage of pulse corona and load impedance on increasing electrode length were decreased. These results indicate we can control critical voltage of pulse corona and suppress arc discharging between two electrodes.

• 전력전자학회논문지
• /
• 제8권6호
• /
• pp.585-592
• /
• 2003

The parallel operation system of UPS is used to increase reliability of power source at critical load. But parallel UPS system has a few defects, impedance is different from each other and circulating current occurs between UPSs, due to line impedance and parameter variation, though controlled by the same synchronization signal. According to such characteristic of parallel UPS, balanced load-sharing control is the most important technique in parallel UPS operation. In this paper, a novel power deviation compensation algorithm is proposed. it is composed of voltage controller to compensate power deviation that be calculated by using active and reactive current deviation between Inverters on synchronous d-q reference frame.

• 한국전자파학회논문지
• /
• 제29권7호
• /
• pp.484-490
• /
• 2018

본 논문은 13.56 MHz 임피던스 자동 정합 시스템 내의 VI 센서를 이용하여 전압 신호와 전류 신호를 측정하고, 부하임피던스를 계산하는 새로운 알고리즘에 대해서 기술하였다. 기존의 $50{\Omega}$ 교정 부하로 하던 방식에서 벗어나 임의의 복소수 교정 부하를 사용하여 에러율이 향상되는 알고리즘을 제안한다. 에러율은 $R_{IN}$ 평균 1 % 이하, $X_{IN}$은 평균 20 %이하 목표로 한다. 일차적으로 믹서를 사용하여 IF 주파수를 계산하여 에러율을 줄였고, 두 번째로 임의의 복소수 부하를 교정 부하로 사용하였을 때 에러율이 $R_{IN}$은 평균 2.7 %에서 평균 0.3 %로 감소하였고, $X_{IN}$은 평균 102 %에서 평균 18.3%까지 감소하였습니다.

• 대한전자공학회논문지
• /
• 제5권1호
• /
• pp.13-25
• /
• 1968

고주파용 transistor를 이용한 광대역증폭기를 hybrid-π 등가회로를 이용하여 상세하게 분석하였다. 저주파와 고주파의 경우에 관한 해석을 하였고 이득과 대역폭및 입력 impedance와 출력 impedance를 주는 식을 유도하였다. 직렬궤환증폭기는 전압원으로 구동하여야하며 저저항부하로 동작시켜야 하고 병렬궤환증폭기는 전류원으로 구동하여야 하며 고저항부하로 동작시켜야 하는 것을 표시하였고 이 두가지 증폭단은 완충증폭단이나 변압기결합을 하지않고 결합시킬 수 있음을 표시하였다.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2009년도 제40회 하계학술대회
• /
• pp.239_240
• /
• 2009

This paper presents the brief analytical study on 돋 effects of higher impedance transformer(HIT) to reduce distribution system fault current. With the increase of source and load capacity of power system, fault current of D/L is much more increased and, conventional protection equipment-such as sectionalizer and recloser, have to be replaced higher switching capacity. However, this replacements needs a lot of budget to utility. Increase of transformer impedance is can be a countermeasure in practical basis. This paper compares the voltage and fault current magnitude of both cases -%Zt=20% and %Zt2=33.3%(transformer capacity is 75/100MVA). The simulation results show that the steady state voltage of HIT is dropped 5~6% more in peak load, and fault current was decreased about 5kA by high impedance on transformer.

• 대한전자공학회논문지
• /
• 제10권4호
• /
• pp.74-79
• /
• 1973

부성 저항을 갖는 다이오드를 사용한 마이크로파 발진기에서 최대의 출력을 내기 위한 임피이던스 정합조건이 공진기의 load 임피이던스가 다이오드 입피이던스의 1/2이라는 결과가 이론적으로 추출된다. 이 사실을 실험적으로 규명하기 위하여 임페트 다이오드의 임피이던스를 실험적으로 조사하고 마이크로와 공진기를 설계 제작하여 조사하였다.

• 정보학연구
• /
• 제8권3호
• /
• pp.25-33
• /
• 2005

This paper describe a method for measuring line impedance as a function of frequency for an energized powerline in normal operation. A small sinusoidal signal of a powerline communication utility frequency 30khz$\sim$1Mhz band is continuously injected into the line, and a implemented impedance analyzer calculates the indoor powerline channel impedance from the measured magnitude and phase of resulting voltage and current. The impedance measurement is executed over a range of frequencies to produce a wideband impedance versus frequency characteristic. Implemented impedance analyzer can analysis powerline communication environments measuring line impedance due to load caused in indoor. And measured analysis information through the database can use to evaluate performance of modem and to decide test environment standard.