• Journal of the Semiconductor & Display Technology
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• v.10 no.4
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• pp.15-20
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• 2011

The lithography system installed inside precision industry's (e.g. TFT-LCD) production factories are increasing in size, thereby increasing its dynamic load along with it. Such condition causes vibration within the area where the system is installed, which then negatively affects the production line to produce defective products. To prevent this type of situation, the facilities should adopt dynamic design that considers the lithography system's dynamic load. This study predicts the maximum value allowed for dynamic stiffness (which is a ratio of vibration response against a single unit of the dynamic load) of the lithography system and explains the result of its application on actual structures inside the facilities.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.12-18
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• 2020

In semiconductor manufacturing, defect detection is critical to maintain high yield. Currently, computer vision systems used in semiconductor photo lithography still have adopt to digital image processing algorithm, which often occur inspection faults due to sensitivity to external environment. Thus, we intend to handle this problem by means of using Mask R-CNN instead of digital image processing algorithm. Additionally, Mask R-CNN can be trained with image dataset pre-processed by means of the specific designed digital image filter to extract the enhanced feature map of Convolutional Neural Network (CNN). Our approach converged advantage of digital image processing and instance segmentation with deep learning yields more efficient semiconductor photo lithography inspection system than conventional system.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.555-556
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• 2006

In this paper, we have proposed a novel process using two-step electron beam lithography to fabricate 20 nm T-gates for high performance MODFETs. Two-step lithography reduces electron forward scattering by defining the foot on a thin (100 nm) bottom-layer of polymethyl methacrylate (PMMA) at the second step, the T-gate head having been developed at the first step. Adopting a low temperature development technique for the second step reduces the detrimental effect of head exposure on foot definition. We have shown that 20 nm T-gate can be patterned with this process.

• Journal of information and communication convergence engineering
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• v.13 no.1
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• pp.56-61
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• 2015

The demand for high-aspect-ratio structures has been increasing in the field of semiconductors and other applications. Here, we present the commercially available negative-tone SU-8 as a potential resist that can be used for direct patterning of high-aspect-ratio structures at the submicron scale and the nanoscale. Such resist patterns can be used as polymeric molds to create high-aspect-ratio metallic submicron and nanoscale structures by using electroplating. Compared with poly (methyl methacrylate) (PMMA), we found that the negative tone resist required an exposure dose that was less than that of PMMA of equal thickness by a factor of 100-150. Patterning of up to 4:1 aspect ratio SU-8 structures with a minimum feature size of 500 nm was demonstrated. In addition, nanoimprint lithography was studied to further extend the aspect ratio to realize a minimum feature size of less than 10 nm with an extremely high aspect ratio in the negative resist.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.2092-2094
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• 2000

As a next generation lithography (NGL) technology for VLSI semiconductor fabrication, electron beam, ion beam, X-ray and extreme ultraviolet(EUV) are considered as possible candidates. Among these methods, EUV lithography(EUVL) is thought to be the most probable because it is easily realized by improving current optical lithography technology. In order to set EUV radiation which can be applied to EUVL, it is essential to generate very high density and high temperature plasma stably. The method using a pulse power laser and a high voltage pulse discharge is commonly used to accomplish such a high density and high temperature plasma. In this paper we review the recent trends of the EUV generation technique by high density and high temperature plasma.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.18 no.6
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• pp.558-564
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• 2009

To aim at obtaining a correct and fine small pattern by an electron beam lithography several conditions and methods affecting a real pattern shape needs to be investigated. A micro/nano sized pattern shape is sometimes dependent on the scanning method. In this work, four types of scanning methods are implemented and their characteristics are investigated. For a $11\times11um$ pattern, a Zigzag scanning method proves a precise pattern generation. The other ways such as SEM scanning and swirl in-out scanning method result in some distorted pattern shape. It is proved that abrupt change in the pattern generation limits to obtaining a fine and small pattern.

• Journal of the Semiconductor & Display Technology
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• v.12 no.2
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• pp.93-98
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• 2013

Nanoimprint lithography (NIL) is a next generation technology for fabrication of micrometer and nanometer scale patterns. There have been considerable attentions on NIL due to its potential abilities that enable cost-effective and high-throughput nanofabrication to the display device and semiconductor industry. To successfully imprint a nanosized pattern with the thermal NIL, the process conditions such as temperature and pressure should be appropriately selected. This starts with a clear understanding of polymer material behavior during the thermal NIL process. In this paper, a filling process of the polymer resist into nanometer scale cavities during the thermal NIL at the temperature range, where the polymer resist shows the viscoelastic behaviors with consideration of stress relaxation effect of the polymer. In the simulation, the filling process and the residual layer formation are numerically investigated. And the effects of pressure and temperature on NIL process, specially the residual layer formation are discussed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.61-69
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• 2014

With the extreme ultraviolet (EUV) lithography, the performance limit of chemically amplified resists has recently been extended to 16- and 11-nm nodes. However, the line edge roughness (LER) and the line width roughness (LWR) are not reduced automatically with this performance extension. In this paper, to investigate the impacts of the EUVL mask and the EUVL exposure process on LER, EUVL is modeled using multilayer-thin-film theory for the mask structure and the Monte Carlo (MC) method for the exposure process. Simulation results demonstrate how LERs of the mask transfer to the resist and the exposure process develops the resist LERs.

• Journal of the Optical Society of Korea
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• v.16 no.3
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• pp.221-227
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• 2012

We propose optical proximity corrections (OPCs) for digital micromirror device (DMD)-based maskless lithography. A pattern writing scheme is analyzed and a theoretical model for obtaining the dose distribution profile and resulting structure is derived. By using simulation based on this model we were able to reduce the edge placement error (EPE) between the design width and the critical dimension (CD) of a fabricated photoresist, which enables improvement of the CD. Moreover, by experiments carried out with the parameter derived from the writing scheme, we minimized the corner-rounding effect by controlling light transmission to the corners of a feature by modulating a DMD.

• Journal of information and communication convergence engineering
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• v.10 no.3
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• pp.295-299
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• 2012

Defect generation during organic bottom anti-reflective coating (BARC) in the photo lithography process is closely related to humidity control in the BARC coating unit. Defects are related to the water component due to the humidity and act as a blocking material for the etching process, resulting in an extreme pattern bridging in the subsequent BARC etching process of the poly etch step. In this paper, the lower limit for the humidity that should be stringently controlled for to prevent defect generation during BARC coating is proposed. Various images of defects are inspected using various inspection tools utilizing optical and electron beams. The mechanism for defect generation only in the specific BARC coating step is analyzed and explained. The BARC defect-induced gate pattern bridging mechanism in the lithography process is also well explained in this paper.