• 대한임베디드공학회논문지
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• 제14권4호
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• pp.219-226
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• 2019

One of the most widely studied protocols for tactical ad-hoc networks is Optimized Link State Routing Protocol (OLSR). As for OLSR research, most research work focus on reducing control traffic overhead and choosing relay point. In addition, because OLSR is mostly dependent on link detection and propagation, dynamic Hello timer become research challenges. However, different timer interval causes imbalance of link validity time by affecting link lifetime. To solve this problem, we propose a weighted topology graph model for constructing a robust network topology based on the link validity time. In order to calculate the link validity time, we use control message timer, which is set for each node. The simulation results show that the proposed mechanism is able to achieve high end-to-end reliability and low end-to-end delay in small networks.

• 한국컴퓨터정보학회논문지
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• 제17권5호
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• pp.49-57
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• 2012

본 논문에서는 P2P스트리밍에서 peer간 연결 정보를 이용하는 방법을 기반으로 topology 최적화를 연구한다. 제안하는 방법은 mesh-network에서 사용된 link와 사용되지 않은 link의 수로 peer의 업로드 용량을 추정하는 방법을 기반으로 한다. 연결된 link의 정보를 사용하는 기존 방법은 peer의 자원 관리 측면에서 메시지 과부하를 줄이는데 효과적이다. 하지만 업로드 대역폭이 고려되지 않는 topology를 구성할 우려가 있다. 또한 서버에 가까운 peer에서 네트워크 오류 발생시 네트워크 전송성능이 저하될 수 있다. 본 논문에서는 기존 방법의 단점을 보완하는 방법을 제안한다. 기존 방법과 제안하는 방법을 시뮬레이션 하고 결과를 비교 분석한다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.832-841
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• 2016

The voltage-frequency island (VFI) design paradigm has strong potential for achieving high energy efficiency in communication centric manycore system-on-chip (SoC) design called network-on-chip (NoC). However, because of the diminished scaling of wire-dimension and supply voltage as well as threshold voltage in modern CMOS technology, the vulnerability to link failure in VFI NoC is becoming a crucial challenge. In this paper, we propose an energy-optimized topology generation technique for VFI NoC to cope with permanent link failures. Based on the energy consumption model, we exploit the on-chip communication traffic patterns and characteristics of link failures in the early design stage to accommodate diverse applications and architectures. Experimental results using a number of multimedia application benchmarks show the effectiveness of the proposed three-step custom topology generation method in terms of energy consumption and latency without any degradation in the fault coverage metric.

• 한국컴퓨터정보학회논문지
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• 제1권1호
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• pp.25-36
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• 1996

본 논문은 격자 구조 회선 교환 망에서 발생할 수 있는 호 차단 확률 및 failure model을 설정하여 신뢰도를 분석하였다 특히 failure model에서는 link failure 모델을 고려하였다. 대상 모델은.flooding search routing 방식을 사용하여 패킷을 통화 대상자 노드에 전송하였다. 이때. 각 링크failure는 독립적이라고 가정하였다. 이와 같은 failure모델의 성능을 평가하기 위한 방법으로서 joint probability를 이용하여 소규모 격자 구조 회선 교환망의 신뢰도를 분석해 보았으며. 이를 시뮬레이션 한 값과 비교해 보았다 또한. 통신망에서 주요한 성능 지표중 하나8! 호 차단 확률을 구하여 회선망의 신뢰도를 평가하였다.

• Journal of Power Electronics
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• 제18권5호
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• pp.1315-1324
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• 2018

A novel three-phase four-wire inverter topology is presented in this paper. This topology is equipped with a special capacitor balance grid without magnetic saturation. In response to unbalanced load and unequal split DC-link capacitors problems, a qusi-full-bridge DC/DC topology is applied in the balance grid. By using a high-frequency transformer, the energy transfer within the two split dc-link capacitors is realized. The novel topology makes the voltage across two split dc-link capacitors balanced so that the neutral point voltage ripple is inhibited. Under the condition of a stable neutral point voltage, the three-phase four-wire inverter can be equivalent to three independent single phase inverters. As a result, the three-phase inverter can produce symmetrical voltage waves with an unbalanced load. To avoid forward transformer magnetic saturation, the voltages of the primary and secondary windings are controlled to reverse once during each switching period. Furthermore, an improved mode chosen operating principle for this novel topology is designed and analyzed in detail. The simulated results verified the feasibility of this topology and an experimental inverter has been built to test the power quality produced by this topology. Finally, simulation results verify that the novel topology can effectively improve the inhibition of an inverter with a three-phase unbalanced load while decreasing the value of the split capacitor.

• 정보처리학회논문지A
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• 제8A권2호
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• pp.157-166
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• 2001

A simulation package has been developed as an event-driven system that can handle the hardware configuration of STC104 and algorithm proposed in the sister paper of ‘Study on High Speed Routers(II).’After various STC104 topology of meshes, torus, and hypercubes are constructed using up to 512 switches, the performance of each topology has been analyzed under different message generation rate in terms of throughputs, latency, and packet blocking time. Modified multicast algorithms for STC104 have been proposed for STC104 after U-mesh and U-torus in order to overcome the multicasting difficulty because of the point-to-point communication method found in STC104. The performance of the multicast algorithms have been analyzed over meshes and torus configuration. Throughput gets higher in the order of mesh, torus, and hypercube. Throughput difference among topology were distinctive in the zone of high message generation rate. Latency and blocking time increased in the order of hypercube, torus, and mesh. U-mesh and U-torus of software multicast showed similar throughput, however, U-mesh peformed slightly better result. These algorithms showed eight to ten times better results compared to individual message pass for 90 destination nodes. Multi-link environment also showed better performance than single-link environment because multi-link network used the extra links for communication.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2013년도 추계학술대회 논문집
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• pp.111-112
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• 2013

The three-phase four-leg voltage source inverter (VSI) topology can be an interesting option for the three phase-four wire system. With an additional leg, this topology can handle the neutral current, hence the DC link capacitance can be reduced significantly. In this paper the three dimensional space vector modulation (3D SVM) in ${\alpha}{\beta}{\gamma}$ coordinates for the three-phase four-leg VSI is presented. By using the 3D SVM method, the DC link voltage can be reduced by 16% compared with the split DC link capacitor topology and the output distortion can also be reduced under the unbalanced load condition.

• Journal of Power Electronics
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• 제16권4호
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• pp.1504-1512
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• 2016

This paper presents a new single-phase asymmetrical cascaded multilevel DC-link inverter. The proposed inverter comprises two stages. The main stage of the inverter consists of multiple similar cells, each of which is a half-bridge inverter consisting of two switches and a single DC source. All cells are connected in a cascaded manner with a fixed neutral point. The DC source values are not made equal to increase the performance of the inverter. The second circuit is a folded cascaded H-bridge circuit operating at a line frequency. One of the main advantages of this proposed topology is that it is a modular type and can thus be extended to high stages without changing the configuration of the main stage circuit. Two control schemes, namely, low switching with selective harmonic elimination and sinusoidal pulse width modulation, are employed to validate the proposed topology. The detailed approach of each control scheme and switching pulses are discussed in detail. A 150W prototype of the proposed system is implemented in the laboratory to verify the validity of the proposed topology.

• 산업공학
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• 제16권spc호
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• pp.14-20
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• 2003

This paper presents a multi-criteria decision model and Multi-Criteria Generic Algorithm(MCGA) approach to improve backbone topology by leveraging the Virtual Link(VL) system in an hierarchical Link-State(LS) routing domain. Given that the sound backbone topology structure has a great impact on the overall routing performance in an hierarchical LS domain, the importance of this research is evident. The proposed decision model is to find an optimal configuration of VLs that properly meets two-pronged engineering goals in installing and maintaining VLs: i.e., operational costs and network reliability. The experiment results clearly indicates that it is essential to the effective operations of hierarchical LS routing domain to consider not only engineering aspects but also specific benefits from systematical layout of VLs, thereby presenting the validity of the decision model and MCGA.

• 전자공학회논문지
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• 제53권8호
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• pp.49-58
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• 2016

어플리케이션 특성에 따라 링크 대역폭 요구량이 다양하게 분포하는 이종 (heterogeneous) 아키텍처 기반 네트워크-온-칩 (Network-on-Chip, NoC) 설계에 있어 링크 지연 시간이 독립적으로 설정될 수 있는 비동기식 프로토콜을 적용할 경우 동기식 설계에 비해 성능 향상의 기회가 확대될 수 있다. 본 논문에서는 비동기식 NoC에서 각 링크의 대역폭 요구량과 도선 길이에 따른 지연 시간 모델을 제시하고 이를 최적화하는 simulated annealing (SA) 기법을 이용한 플로어플랜 기반 토폴로지 생성 알고리즘을 제안하였다. 생성된 토폴로지와 각 링크의 도선 길이를 기반으로 대응하는 도선 지연시간을 계산하고 로직 합성 단계를 거쳐 생성된 gate-level netlist와 표준지연시간 모델을 이용한 시뮬레이션을 통해 성능을 측정하였다. 링크 도선 길이를 고려하지 않은 일반적인 토폴로지 생성 알고리즘인 TopGen과 비교하여, 제안된 알고리즘이 다양한 어플리케이션 실험에서 평균 13.7% 지연 시간 단축 효과 및 처리량 측면 지표인 실행 시간에서 평균 11.8% 감소 효과가 있음을 확인할 수 있었다.