• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.4
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• pp.219-226
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• 2019

One of the most widely studied protocols for tactical ad-hoc networks is Optimized Link State Routing Protocol (OLSR). As for OLSR research, most research work focus on reducing control traffic overhead and choosing relay point. In addition, because OLSR is mostly dependent on link detection and propagation, dynamic Hello timer become research challenges. However, different timer interval causes imbalance of link validity time by affecting link lifetime. To solve this problem, we propose a weighted topology graph model for constructing a robust network topology based on the link validity time. In order to calculate the link validity time, we use control message timer, which is set for each node. The simulation results show that the proposed mechanism is able to achieve high end-to-end reliability and low end-to-end delay in small networks.

• Journal of the Korea Society of Computer and Information
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• v.17 no.5
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• pp.49-57
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• 2012

In P2P streaming management, peer's churning and finding efficient topology architecture optimization algorithm that reduces streaming delay is important. This paper studies a topology optimization algorithm based on the P2P streaming using peer's link information. The proposed algorithm is based on the estimation of peer's upload bandwidth using peer's link information on mesh-network. The existing algorithm that uses the information of connected links is efficient to reduce message overload in the point of resource management. But it has a risk of making unreliable topology not considering upload bandwidth. And when some network error occurs in a server-closer-peer, it may make the topology worse. In this paper we propose an algorithm that makes up for the weak point of the existing algorithm. We compare the existing algorithm with the proposed algorithm using test data and analyze each simulation result.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.832-841
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• 2016

The voltage-frequency island (VFI) design paradigm has strong potential for achieving high energy efficiency in communication centric manycore system-on-chip (SoC) design called network-on-chip (NoC). However, because of the diminished scaling of wire-dimension and supply voltage as well as threshold voltage in modern CMOS technology, the vulnerability to link failure in VFI NoC is becoming a crucial challenge. In this paper, we propose an energy-optimized topology generation technique for VFI NoC to cope with permanent link failures. Based on the energy consumption model, we exploit the on-chip communication traffic patterns and characteristics of link failures in the early design stage to accommodate diverse applications and architectures. Experimental results using a number of multimedia application benchmarks show the effectiveness of the proposed three-step custom topology generation method in terms of energy consumption and latency without any degradation in the fault coverage metric.

• Journal of the Korea Society of Computer and Information
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• v.1 no.1
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• pp.25-36
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• 1996

We have analyzed the reliability of failure models In grid topology circuit switched networks. These models are grid topology circuit_ switched networks. and each node transmits packets to object node using flooding search routing method. We hypothesized that the failure of each link Is Independent. We have analyzed for the performance estimation of failure models It using joint probability method to the reliability of a small grid topology circuit switched network. and compared analytic output with simulated output. Also. We have evaluated the reliability of networks using call blocking Probability occurred in circuit switched networks.

• Journal of Power Electronics
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• v.18 no.5
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• pp.1315-1324
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• 2018

A novel three-phase four-wire inverter topology is presented in this paper. This topology is equipped with a special capacitor balance grid without magnetic saturation. In response to unbalanced load and unequal split DC-link capacitors problems, a qusi-full-bridge DC/DC topology is applied in the balance grid. By using a high-frequency transformer, the energy transfer within the two split dc-link capacitors is realized. The novel topology makes the voltage across two split dc-link capacitors balanced so that the neutral point voltage ripple is inhibited. Under the condition of a stable neutral point voltage, the three-phase four-wire inverter can be equivalent to three independent single phase inverters. As a result, the three-phase inverter can produce symmetrical voltage waves with an unbalanced load. To avoid forward transformer magnetic saturation, the voltages of the primary and secondary windings are controlled to reverse once during each switching period. Furthermore, an improved mode chosen operating principle for this novel topology is designed and analyzed in detail. The simulated results verified the feasibility of this topology and an experimental inverter has been built to test the power quality produced by this topology. Finally, simulation results verify that the novel topology can effectively improve the inhibition of an inverter with a three-phase unbalanced load while decreasing the value of the split capacitor.

• The KIPS Transactions:PartA
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• v.8A no.2
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• pp.157-166
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• 2001

A simulation package has been developed as an event-driven system that can handle the hardware configuration of STC104 and algorithm proposed in the sister paper of ‘Study on High Speed Routers(II).’After various STC104 topology of meshes, torus, and hypercubes are constructed using up to 512 switches, the performance of each topology has been analyzed under different message generation rate in terms of throughputs, latency, and packet blocking time. Modified multicast algorithms for STC104 have been proposed for STC104 after U-mesh and U-torus in order to overcome the multicasting difficulty because of the point-to-point communication method found in STC104. The performance of the multicast algorithms have been analyzed over meshes and torus configuration. Throughput gets higher in the order of mesh, torus, and hypercube. Throughput difference among topology were distinctive in the zone of high message generation rate. Latency and blocking time increased in the order of hypercube, torus, and mesh. U-mesh and U-torus of software multicast showed similar throughput, however, U-mesh peformed slightly better result. These algorithms showed eight to ten times better results compared to individual message pass for 90 destination nodes. Multi-link environment also showed better performance than single-link environment because multi-link network used the extra links for communication.

• Proceedings of the KIPE Conference
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• 2013.11a
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• pp.111-112
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• 2013

The three-phase four-leg voltage source inverter (VSI) topology can be an interesting option for the three phase-four wire system. With an additional leg, this topology can handle the neutral current, hence the DC link capacitance can be reduced significantly. In this paper the three dimensional space vector modulation (3D SVM) in ${\alpha}{\beta}{\gamma}$ coordinates for the three-phase four-leg VSI is presented. By using the 3D SVM method, the DC link voltage can be reduced by 16% compared with the split DC link capacitor topology and the output distortion can also be reduced under the unbalanced load condition.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1504-1512
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• 2016

This paper presents a new single-phase asymmetrical cascaded multilevel DC-link inverter. The proposed inverter comprises two stages. The main stage of the inverter consists of multiple similar cells, each of which is a half-bridge inverter consisting of two switches and a single DC source. All cells are connected in a cascaded manner with a fixed neutral point. The DC source values are not made equal to increase the performance of the inverter. The second circuit is a folded cascaded H-bridge circuit operating at a line frequency. One of the main advantages of this proposed topology is that it is a modular type and can thus be extended to high stages without changing the configuration of the main stage circuit. Two control schemes, namely, low switching with selective harmonic elimination and sinusoidal pulse width modulation, are employed to validate the proposed topology. The detailed approach of each control scheme and switching pulses are discussed in detail. A 150W prototype of the proposed system is implemented in the laboratory to verify the validity of the proposed topology.

• IE interfaces
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• v.16 no.spc
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• pp.14-20
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• 2003

This paper presents a multi-criteria decision model and Multi-Criteria Generic Algorithm(MCGA) approach to improve backbone topology by leveraging the Virtual Link(VL) system in an hierarchical Link-State(LS) routing domain. Given that the sound backbone topology structure has a great impact on the overall routing performance in an hierarchical LS domain, the importance of this research is evident. The proposed decision model is to find an optimal configuration of VLs that properly meets two-pronged engineering goals in installing and maintaining VLs: i.e., operational costs and network reliability. The experiment results clearly indicates that it is essential to the effective operations of hierarchical LS routing domain to consider not only engineering aspects but also specific benefits from systematical layout of VLs, thereby presenting the validity of the decision model and MCGA.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.49-58
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• 2016

In designing heterogeneous architecture based application-specific network-on-chips (NoCs), the opportunities of performance improvement would be expanded when applying asynchronous on-chip communication protocol. This is because the wire latency can be configured independently considering the wirelength of each link. In this paper, we develop the delay model of link-wire-length in asynchronous NoC and propose simulated annealing (SA) based floorplan-aware topology generation algorithm to optimize link-wirelengths. Incorporating the generated topology and the associated latency values across all links, we evaluate the performance using the floorplan-annotated sdf (standard delay format) file and RTL-synthesized gate-level netlist. Compared to TopGen, one of general topology generation algorithms, the experimental results show the reduction in latency by 13.7% and in execution time by 11.8% in average with regards to four applications.