• 제목/요약/키워드: linear resistor

검색결과 65건 처리시간 0.023초

Simple one-step synthesis of carbon nanoparticles from aliphatic alcohols and n-hexane by stable solution plasma process

  • Park, Choon-Sang;Kum, Dae Sub;Kim, Jong Cheol;Shin, Jun-Goo;Kim, Hyun-Jin;Jung, Eun Young;Kim, Dong Ha;Kim, Daseulbi;Bae, Gyu Tae;Kim, Jae Young;Shin, Bhum Jae;Tae, Heung-Sik
    • Carbon letters
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    • 제28권
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    • pp.31-37
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    • 2018
  • This paper examines a simple one-step and catalyst-free method for synthesizing carbon nanoparticles from aliphatic alcohols and n-hexane with linear molecule formations by using a stable solution plasma process with a bipolar pulse and an external resistor. When the external resistor is adopted, it is observed that the current spikes are dramatically decreased, which induced production of a more stable discharge. Six aliphatic linear alcohols (methanol-hexanol) containing carbon with oxygen sources are studied as possible precursors for the massive production of carbon nanoparticles. Additional study is also carried out with the use of n-hexane containing many carbons without an oxygen source in order to enhance the formation of carbon nanoparticles and to eliminate unwanted oxygen effects. The obtained carbon nanoparticles are characterized with field emission-scanning electron microscopy, energy dispersive X-ray spectroscopy, and Raman spectroscopy. The results show that with increasing carbon ratios in alcohol content, the synthesis rate of carbon nanoparticles is increased, whereas the size of the carbon nanoparticles is decreased. Moreover, the degree of graphitization of the carbon nanoparticles synthesized from 1-hexanol and n-hexane with a high carbon (C)/oxygen (O) ratio and low or no oxygen is observed to be greater than that of the carbon nanoparticles synthesized from the corresponding materials with a low C/O ratio.

Low-Voltage Tunable Pseudo-Differential Transconductor with High Linearity

  • Galan, Juan Antonio Gomez;Carrasco, Manuel Pedro;Pennisi, Melita;Martin, Antonio Lopez;Carvajal, Ramon Gonzalez;Ramirez-Angulo, Jaime
    • ETRI Journal
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    • 제31권5호
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    • pp.576-584
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    • 2009
  • A novel tunable transconductor is presented. Input transistors operate in the triode region to achieve programmable voltage-to-current conversion. These transistors are kept in the triode region by a novel negative feedback loop which features simplicity, low voltage requirements, and high output resistance. A linearity analysis is carried out which demonstrates how the proposed transconductance tuning scheme leads to high linearity in a wide transconductance range. Measurement results for a 0.5 ${\mu}m$ CMOS implementation of the transconductor show a transconductance tuning range of more than a decade (15 ${\mu}A/V$ to 165 ${\mu}A/V$) and a total harmonic distortion of -67 dB at 1 MHz for an input of 1 Vpp and a supply voltage of 1.8 V.

CMOS 게이트에 의해서 구동되는 배선 회로의 타이밍 특성 분석 (Analysis of timing characteristics of interconnect circuits driven by a CMOS gate)

  • 조경순;변영기
    • 전자공학회논문지C
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    • 제35C권4호
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    • pp.21-29
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    • 1998
  • As silicon geometry shrinks into deep submicron and the operating speed icreases, higher accuracy is required in the analysis of the propagation delays of the gates and interconnects in an ASIC. In this paper, the driving characteristics of a CMOS gate is represented by a gatedriver model, consisting of a linear resistor $R_{dr}$ and an independent ramp voltage source $V_{dr}$ . We drivered $R_{dr}$ and $V_{dr}$ as the functions of the timing data representing gate driving capability and an effective capacitance $C_{eff}$ reflecting resistance shielding effect by interconnet circuits. Through iterative applications of these equations and AWE algorithm, $R_{dr}$ , $V_{dr}$ and $C_{eff}$ are comuted simulataneously. then, the gate delay is decided by $C_{eff}$ and the interconnect circuit delay is determined by $R_{dr}$ and $V_{dr}$ . this process has been implemented as an ASIC timing analysis program written in C language and four real circuits were analyzed. In all cases, we found less than 5% of errors for both of gate andinterconnect circuit delays with a speedup factor ranging from a few tens to a few hundreds, compared to SPICE.SPICE.

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Piezoelectric PZT Cantilever Array Integrated with Piezoresistor for High Speed Operation and Calibration of Atomic Force Microscopy

  • Nam, Hyo-Jin;Kim, Young-Sik;Cho, Seong-Moon;Lee, Caroline-Sunyong;Bu, Jong-Uk;Hong, Jae-Wan
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제2권4호
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    • pp.246-252
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    • 2002
  • Two kinds of PZT cantilevers integrated with a piezoresistor have been newly designed, fabricated, and characterized for high speed AFM. In first cantilever, a piezoresistor is used to sense atomic force acting on tip, while in second cantilever, a piezoresistor is integrated to calibrate hysteresis and creep phenomena of the PZT cantilever. The fabricated PZT cantilevers provide high tip displacement of $0.55\mu\textrm{m}/V$ and high resonant frequency of 73 KHz. A new cantilever structure has been designed to prevent electrical coupling between sensor and PZT actuator and the proposed cantilever shows 5 times lower coupling voltage than that of the previous cantilever. The fabricated PZT cantilever shows a crisp scanned image at 1mm/sec, while the conventional piezo-tube scanner shows blurred image even at $180\mu\textrm{m}/sec$. The non-linear properties of the PZT actuator are also well calibrated using the piezoresistive sensor for calibration.

탄소 피막 가변 저항기의 접동 잡음 감소에 관한 연구 (A Study on Decreasing of Sliding Noise of a Carbon Film Variable Resistor)

  • 윤재강
    • 대한전자공학회논문지
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    • 제20권1호
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    • pp.50-54
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    • 1983
  • 민생용 전자기기에서 가장 많이 사용되고 있는 부품중의 하나인 탄소 피막 가변 저항기에서 접동자 이동시 발생하는 접촉 저항 변화의 원인을 분석하여 이에 대한 감소, 즉 접동 잡음 감소를 위한 몇 가지 방법을 착안하여 실험 검토하고 그 결과을 정리하여 본 결과 균일한 크기를 가진 탄소 분말 입자로서 고루게 배합된 저항액을 사용하고 접동자의 접촉점과 압력을 증가하면 접촉 저항 및 접촉 저항 변화. 즉 잠동 잡음을 감소시킬 수 있다.

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연속시간의 MOSFET-C 필터 설계 (The Design of Continuous-Time MOSFET-C Filter)

  • 최석우;윤창훈;조성익;조해풍;이종인;김동용
    • 한국통신학회논문지
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    • 제18권2호
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    • pp.184-191
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    • 1993
  • 최근 MOS 공정기술로 집적화된 연속시간 필터 연구가 주목을 받고 있다. 본 논문에서는 차단주파수 3,400Hz를 갖는 연속시간 5차 타원 저역통과 MOSFET-C 필터를 실현하기 위하여, 먼저 각 블록을 동조할 수 있는 종속연결법으로 능동 RC 필터를 설계하였다. 그리고 능동 RC 회로의 저항들을 triode 영역에서 작동하는 NMOS depletion mode 트랜지스터 선형저항으로 실현하였다. 이러한 연속시간 MOSFET-C 필터는 스윗치드 커패시터 필터에 비하여 구조가 간단하여 칩의 면적을 줄일 수 있다. 설계된 MOSFET-C 필터 특성을 PSPICE 프로그램으로 시뮬레이션 하였다.

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$Al^{3+}$ 이온이 첨가된 ZnO 반도체 가스 센서의 전기적 특성에 관한 연구 (A Study on the Electrical Characterisitics of $Al^{3+}$-doped ZnO Semiconductor Gas Sensor)

  • 정의남;이건형;김종대;김창욱
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1987년도 정기총회 및 창립40주년기념 학술대회 학회본부
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    • pp.245-247
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    • 1987
  • In this thesis, ZnO semiconductor gas sensors doped by the $Al^{3+}$ were fabricated by the miexed oxide method. The specimens were sintered for 5(hr) at $1000-1200^{\circ}C$ and the I-V, sensitivity were investigated in acetone gas or ammonia gas. As a result, I-V curves of specimens as a function of temperature variation showed characteristics of linear resistor that the current was proportional to the, temperature at constant voltage. For the sensitivity of acetone, 1Wt $Al^{3+}$-ZnO has the hight 0.91, ammonia gas, 2Wt $Al^{3+}$-ZnO specimen has the hight 0.90. Hence, the operating temperature of specimens were both $300^{\circ}C$.

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범용 회로 시뮬레이터를 위한 손실을 반영한 PCB 평판 모형 (PCB Plane Model Including Frequency-Dependent Losses for Generic Circuit Simulators)

  • 백종흠;정용진;김석윤
    • 대한전자공학회논문지SD
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    • 제41권6호
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    • pp.91-98
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    • 2004
  • 본 논문은 일반적인 SPICE 시뮬레이터에서 사용 가능한 PCB 평판 해석 모형을 제안한다. 제안된 모형은 주파수에 따라 증가하는 두 가지 손실, 즉, 표피 손실과 유전 손실의 영향을 반영한다. 평판은 메시(mesh) 구조로 조각을 낸 후, 각각의 단위모형은 전송선 소자와 손실 모형을 이용하여 모형화된다. 손실 모형은 DC 손실을 위해서 하나의 저항이 요구되고, 표피 손실을 위해 직렬 RL ladder 회로, 유전 손실을 위해서 직렬 RC ladder 회로가 요구된다. 제안된 모형의 검증을 위해 주파수 가변저항을 사용한 SPICE ac 해석결과를 통해 비교하고, 전형적인 데스크탑 PC용 FR4 4층 PCB 적층 구조를 만들어 VNA 측정치와도 비교할 것이다. 이 모형은 RLGC 수동 소자들로만 구성되므로 주파수 영역 및 시간 영역에서도 다양한 선형/비선형 소자들과 결합하여 과도 해석이 가능하다.

새로운 200 MHz CMOS 선형 트랜스컨덕터와 이를 이용한 20 MHz 일립틱 여파기의 설계 (Design of a Novel 200 MHz CMOS Linear Transconductor and Its Application to a 20 MHz Elliptic Filter)

  • 박희종;차형우;정원섭
    • 전자공학회논문지SC
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    • 제38권4호
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    • pp.20-30
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    • 2001
  • 트랜스리니어 셀을 이용한 새로운 200 MHz CMOS 트랜스컨덕터를 제안하였다. 제안한 트랜스컨덕터는 트랜스리니어 셀에 기초를 둔 전압 폴로워 및 전류 폴로워와 하나의 저항기로 구성된다. 트랜스컨덕터의 폭 넓은 응용을 위해, 단일-입력 단일-출력, 단일-입력 차동-출력, 그리고 완전-차동 트랜스컨덕터를 각각 체계적으로 설계하였다. 컴퓨터 시뮬레이션의 결과, 완전-차동 트랜스컨덕터는 ${\pm}3$ V의 공급 전압에서 ${\pm}2.7$ V의 입력 선형 범위, 200 MHz의 3-dB 주파수, 그리고 41 $ppm/^{\circ}C$ 이하의 온도 계수를· 가진다는 것을 확인하였다. 완선-차동 트랜스컨덕터의 응용성을 확인하기 위해, 인덕턴스 시뮬레이션 방식에 기초한 3차 사다리형 일립틱 저역-통과 여파기를 설계하였다. 설계된 저역-통과 여파기는 22 MHz의 리플 대역폭파 0.36 dB의 통과 대역 리플, 그리고 26 MHz의 차단 주파수를 가진다.

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히스테리시스 특성을 고려한 측정용 변류기 보상 알고리즘 (Compensating algorithm for a measurement type CT considering hysteresis characteristic of the core)

  • 강용철;정태영;이병은;소순홍;이현웅;이미선;박정호;최현태;장성일;김용균
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2007년도 제38회 하계학술대회
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    • pp.44-45
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    • 2007
  • This paper deals with error compensation in current transformers. Since the exciting current can be considered as the main error source, its evaluation can allow the compensation of its detrimental effects to be obtained. The exciting current required by the transformer in every king of steady state operation can be determined by simply acquiring the secondary current, provided that the examined CT has been preliminarily identified. This paper also proposed a new approach to the model of the exciting branch. The exciting branch can be divided into a non-linear core loss resistor, and a non-linear magnetizing inductor whose flux and current characteristic is not the same as the characteristic shown by the joined tips of the first quadrant of a family of hysteresis loops. The performance of the proposed algorithm was validated under various conditions using EMTP generated data. Test result show, in all cases an improvement in primary current reproduction accuracy, compared with that achieved using CT's ratio.

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