• Journal of the Korea Institute of Information Security & Cryptology
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• v.33 no.2
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• pp.165-173
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• 2023

In this paper, we propose an optimal implementation of lightweight block ciphers, SIMECK and SIMON counter operation mode, on a 32-bit RISC-V processor. Utilizing the characteristics of the CTR operating mode, we propose round function optimization that precomputes some values, single plaintext optimization and two plaintext parallel optimization. Since there are no previous research results on SIMECK and SIMON on RISC-V, we compared the performance of implementations with and without precomputation techniques for single plaintext optimization and two plaintext parallel optimization implementations. As a result, the implementations to which the precomputation technique was applied showed a performance improvement of 1% compared to the implementations to which precomputation was not applied.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.30 no.3
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• pp.325-336
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• 2020

Nonlinear Invariant Attack is an attack that should be considered when constructing lightweight block ciphers with relatively simple key schedule. A shortcut to prove a block cipher's resistance against nonlinear invariant attack is checking the smallest dimension of linear layer-invariant linear subspace which contains all known differences between round keys is equal to the block size. In this paper, we presents the following results. We identify the structure and number of optimal bit-permutations which require only one known difference between round keys for a designer to show that the corresponding block cipher is resistant against nonlinear invariant attack. Moreover, we show that PRESENT-like block ciphers need at least two known differences between round keys by checking all PRESENT-like bit-permutations. Additionally, we verify that the variants of PRESENT-like bit-permutations requiring the only two known differences between round keys do not conflict with the resistance against differential attack by comparing the best differential trails. Finally, through the distribution of the invariant factors of all bit-permutations that maintain BOGI logic with GIFT S-box, GIFT-variant block ciphers require at least 8 known differences between round keys for the resistance.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.11
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• pp.4502-4521
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• 2020

At EUROCRYPT 2015, Todo proposed a new technique named division property, and it is a powerful technique to find integral distinguishers. The original division property is also named word-based division property. Later, Todo and Morii once again proposed a new technique named the bit-based division property at FSE 2016 and find more rounds integral distinguisher for SIMON-32. There are two basic approaches currently being adopted in researches under the bit-based division property. One is conventional bit-based division property (CBDP), the other is bit-based division property using three-subset (BDPT). Particularly, BDPT is more powerful than CBDP. In this paper, we use Boolean Satisfiability Problem (SAT)-aided cryptanalysis to search integral distinguishers. We conduct experiments on SIMON-32/-48/-64/-96, SIMON (102)-32/-48/-64, SIMECK-32/-48/-64, LBlock, GIFT and Khudra to prove the efficiency of our method. For SIMON (102)-32/-48/-64, we can determine some bits are odd, while these bits can only be determined as constant in the previous result. For GIFT, more balanced (zero-sum) bits can be found. For LBlock, we can find some other new integral distinguishers. For Khudra, we obtain two 9-round integral distinguishers. For other ciphers, we can find the same integral distinguishers as before.

• Proceedings of the Korea Information Processing Society Conference
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• 2022.05a
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• pp.183-186
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• 2022

고성능 양자 컴퓨터가 개발될 것으로 기대됨에 따라 잠재적인 양자 컴퓨터의 공격으로부터 안전한 양자 후 보안 시스템을 구축하기 위한 연구들이 진행되고 있다. 대표적인 양자 알고리즘인 Grover 알고리즘이 대칭키 암호에 적용될 경우 보안 강도가 제곱근으로 감소되는 보안 훼손이 발생한다. NIST는 대칭키 암호에 대한 양자 후 보안 요구사항으로, 암호 알고리즘 공격에 요구되는 Grover 알고리즘 비용을 기준을 기준으로 양자 후 보안 강도를 추정하고 있다. 대칭키 암호를 공격하기 위한 Grover 알고리즘의 비용은 대상 암호화 알고리즘의 양자 회로 복잡도에 따라 결정된다. 본 논문에서는 NIST 경량암호 공모전 최종 후보에 오른 Sparkle 알고리즘의 양자 회로를 효율적으로 구현하고 Grover 알고리즘을 적용하기 위한 양자 비용에 대해 분석한다. 마지막으로, NIST 양자 후 보안 요구사항과 분석한 비용을 기반으로 경량암호 Sparkle에 대한 양자 후 보안 강도를 평가한다. 양자 회로 구현 및 비용 분석에는 양자 프로그래밍 툴인 ProjectQ가 사용되었다.

• Proceedings of the Korea Information Processing Society Conference
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• 2021.05a
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• pp.171-174
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• 2021

최근 사물인터넷(IoT) 환경에서 다양한 장비의 인터넷 통신이 가능하여 이에 적절한 경량 블록 암호 알고리즘에 대한 연구가 활발히 진행되고 있다. ICISC 2020에서 새로 발표된 국산 경량 블록 암호 알고리즘인 PIPO는 새로운 경량 S-Box를 조합한 unbalanced-Bridge 구조로 효율적인 비트슬라이싱 구현을 제공한다. IoT 환경에 PIPO가 적용되기 위해서는 부채널 분석에 대한 안전성이 보장되어야 한다. 따라서 본 논문에서는 PIPO가 1차 CPA 공격에 취약함을 확인한다. 그리고 부채널 공격에 대응하기 위해 1차 마스킹 기법을 제안한다. 제안한 마스킹 기법은 1차 CPA 공격에 안전하였으며, 마스킹 적용 전보다 -375%의 성능을 보였다. 그리고 기존 기법보다 1287% 속도가 빨라진 것을 확인하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2021.11a
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• pp.217-220
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• 2021

ICISC'19에서 기존 CHAM과 동일한 구조와 규격을 갖지만, 라운드 수만 증가시킨 revised CHAM이 발표되었다. CHAM은 사물인터넷에서 사용되는 저사양 프로세서에서 효율적인 구현이 가능한 특징을 갖고 있다. AVR, ARM 프로세서 상에서의 CHAM 암호 알고리즘에 대한 최적 구현은 존재하지만, 아직 RISC-V 프로세서 상에서의 CHAM 구현은 존재하지 않는다. 따라서, 본 논문에서는 RISC-V 프로세서 상에서의 Revised CHAM 알고리즘을 최초로 구현을 제안한다. CHAM 라운드 함수의 내부 구조의 일부를 생략하여 최적 구현하였다. 그리고 홀수 라운드와 짝수 라운드를 모듈별로 구현하여 필요에 따라 모듈을 호출하여 손쉽게 사용할 수 있게 하였다. 결과적으로, RISC-V 상에서 제안 기법 적용하기 전보다 제안 기법 적용 후에 12%의 속도 향상을 달성하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.8
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• pp.1588-1596
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• 2015

In the Internet of Things (IoT), resource-constrained devices such as sensors are capable of communicating and exchanging data over the Internet. The IETF standard group has specified an application protocol CoAP, which uses UDP as a transport protocol, allows such a lightweight device to transmit data. Also, the IETF recommended the DTLS binding for securing CoAP. However, additional features should be added to the DTLS protocol to resolve several problems such as packet loss, reordering, fragmentation and replay attack. Consequently, performance of DTLS is worse than TLS. It is highly required for lightweight devices powered by small battery to design and implement a security protocol in an energy efficient manner. This paper thus discusses about DTLS performance in the perspective of energy consumption. To analyze the performance, we implemented IEEE 802.15.4 based test network consisting of constrained sensor devices in the Cooja simulator. We measured energy consumptions required for each of DTLS client and server in the test network. This paper compares the energy consumption and amount of transmitted data of each flight of DTLS handshake, and the processing and receiving time. We present the analyzed results with regard to code size, cipher primitive and fragmentation as well.

• Journal of IKEEE
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• v.22 no.1
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• pp.38-45
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• 2018

An integrated cryptographic processor that efficiently integrates ARIA, AES block ciphers and Whirlpool hash function into a single hardware architecture is described. Based on the algorithm characteristics of ARIA, AES, and Whirlpool, we optimized the design so that the hardware resources of the substitution layer and the diffusion layer were shared. The round block was designed to operate in a time-division manner for the round transformation and the round key expansion of the Whirlpool hash, resulting in a lightweight hardware implementation. The hardware operation of the integrated ARIA-AES-Whirlpool crypto-processor was verified by Virtex5 FPGA implementation, and it occupied 68,531 gate equivalents (GEs) with a 0.18um CMOS cell library. When operating at 80 MHz clock frequency, it was estimated that the throughputs of ARIA, AES block ciphers, and Whirlpool hash were 602~787 Mbps, 682~930 Mbps, and 512 Mbps, respectively.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.2
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• pp.149-156
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• 2011

In the recent years, power analysis attacks were widely investigated, and so various countermeasures have been proposed. In the case of block ciphers, masking methods that blind the intermediate values in the en/decryption computations are well-known among these countermeasures. But the cost of non-linear part is extremely high in the masking method of block cipher, and so the countermeasure for S-box must be efficiently constructed in the case of AES, ARIA and SEED. Existing countermeasures for S-box use the masked S-box table to require 256 bytes RAM corresponding to one S-box. But, the usage of the these countermeasures is not adequate in the lightweight security devices having the small size of RAM. In this paper, we propose the new countermeasure not using the masked S-box table to make up for this weak point. Also, the new countermeasure reduces time-complexity as well as the usage of RAM because this does not consume the time for generating masked S-box table.

• KIPS Transactions on Computer and Communication Systems
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• v.10 no.8
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• pp.223-230
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• 2021

The lightweight block cipher PIPO announced at ICISC'20 has been effectively implemented by applying the bit slice technique. In this paper, we propose a parallel optimal implementation of PIPO for ARM processors. The proposed implementation enables parallel encryption of 8-plaintexts and 16-plaintexts. The implementation targets the A10x fusion processor. On the target processor, the existing reference PIPO code has performance of 34.6 cpb and 44.7 cpb in 64/128 and 64/256 standards. Among the proposed methods, the general implementation has a performance of 12.0 cpb and 15.6 cpb in the 8-plaintexts 64/128 and 64/256 standards, and 6.3 cpb and 8.1 cpb in the 16-plaintexts 64/128 and 64/256 standards. Compared to the existing reference code implementation, the 8-plaintexts parallel implementation for each standard has about 65.3%, 66.4%, and the 16-plaintexts parallel implementation, about 81.8%, and 82.1% better performance. The register minimum alignment implementation shows performance of 8.2 cpb and 10.2 cpb in the 8-plaintexts 64/128 and 64/256 specifications, and 3.9 cpb and 4.8 cpb in the 16-plaintexts 64/128 and 64/256 specifications. Compared to the existing reference code implementation, the 8-plaintexts parallel implementation has improved performance by about 76.3% and 77.2%, and the 16-plaintext parallel implementation is about 88.7% and 89.3% higher for each standard.