• Journal of dental hygiene science
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• v.24 no.1
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• pp.9-21
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• 2024

Background: The purpose of this study was to utilize text network analysis and topic modeling to identify interconnected relationships among keywords present in patent information related to oral health, and subsequently extract latent topics and visualize them. By examining key keywords and specific subjects, this study sought to comprehend the technological trends in oral health-related innovations. Furthermore, it aims to serve as foundational material, suggesting directions for technological advancement in dentistry and dental hygiene. Methods: The data utilized in this study consisted of information registered over a 20-year period until July 31st, 2023, obtained from the patent information retrieval service, KIPRIS. A total of 6,865 patent titles related to keywords, such as "dentistry," "teeth," and "oral health," were collected through the searches. The research tools included a custom-designed program coded specifically for the research objectives based on Python 3.10. This program was used for keyword frequency analysis, semantic network analysis, and implementation of Latent Dirichlet Allocation for topic modeling. Results: Upon analyzing the centrality of connections among the top 50 frequently occurring words, "method," "tooth," and "manufacturing" displayed the highest centrality, while "active ingredient" had the lowest. Regarding topic modeling outcomes, the "implant" topic constituted the largest share at 22.0%, while topics concerning "devices and materials for oral health" and "toothbrushes and oral care" exhibited the lowest proportions at 5.5% each. Conclusion: Technologies concerning methods and implants are continually being researched in patents related to oral health, while there is comparatively less technological development in devices and materials for oral health. This study is expected to be a valuable resource for uncovering potential themes from a large volume of patent titles and suggesting research directions.

• Journal of Microbiology and Biotechnology
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• v.11 no.6
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• pp.994-1001
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• 2001

An easier way of understanding the BNR system was proposed from the study on substrate, nutrient removal tendency, microbial community and its metabolic function by applying the municipal settled sewage. During the anaerobic period, the phosphorus release rate per VFACOD we varied depending on the phosphorus content in the sludge. When the phosphorus content in the sludge was $6\%$ VSS, according to influent VFACOD, the phosphorus release rate and PHA production were $0.35 gPO_4P/gVFACOD$ and 1.0 gPHA/gVFACOD, respectively. The $NO_3N$ requirement for the phosphorus uptake as an electron acceptor was about $0.5 gNO_3N/gPO_4P_{uptake}$ based on the proposed equation with PHA, biomass, production, and the concentration of phosphorus release/uptake. Bacterial-community analysis of the sludge, as determined by FISH and 16SrDNA characterization FISH, revealed that the beta-subclass proteobacteria were the most abundant group ($27.9\%$ of the proteobacteria-specific probe EUB338), and it was likely that representative of the beta-subclass played key roles in activated sludge. The next dominant group found was the gamma-protebacteria ($15.4\%$ of probe EUB338). 16S rDNA clone library analysis showed that the members of${\beta}$- and ${\gamma}$-proteobacteria were also the most abundant groups, and $21.5\%$ (PN2 and PN4) and $15.4\%$ (PN1 and PN5) of total clones were the genera of denitrifying bacteria and PAO, respectively. Prediction of the microbial community composition was made with phosphorus content (Pv, $\%$ P/VSS) in wasted sludge and profiles of COD, PHA, $PO_4P,\;and\;NO_3N$ in an anaerobic-anoxic SBR unit. Generally, the predicted microbial composition based upon metabolic function, i.e., as measured by stoichiometry, is fairly similar to that measure by the unculturable dependent method. In this study, a proposal was made on he microbial community composition that was more easily approached to analyze the reactor behavior.

• Asian Pacific Journal of Cancer Prevention
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• v.16 no.18
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• pp.8653-8658
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• 2016

Background: Heparanase is believed to be involved in gastric carcinogenesis. However, the clinicopathologic features of gastric cancer with high heparanase expression remain unclear. Aim : The purpose of this study was to comprehensively and quantitatively summarize available evidence for the use of heparanase mRNA and protein expression to evaluate the clinicopathological associations in gastric cancer in Asian patients by meta-analysis. Materials and Methods: Relevant articles listed in MEDLINE, CNKI and the Cochrane Library databases up to MARCH 2015 were searched by use of several keywords in electronic databases. A meta-analysis was performed to clarify the impact of heparanase mRNA and protein on clinicopathological parameters in gastric cancer. Combined ORs with 95%CIs were calculated by Revman 5.0, and publication bias testing was performed by stata12.0. Results: A total of 27 studies which included 3,891 gastric cancer patients were combined in the final analysis. When stratifying the studies by the pathological variables of heparanase mRNA expression, the depth of invasion (633 patients) (OR=4.96; 95% CI=2.38-1.37; P<0.0001), lymph node metastasis (639 patients) (OR=6.22; 95%CI=2.70-14.34, P<0.0001), and lymph node metastasis (383 patients) (OR=6.85; 95% CI=2.04-23.04; P=0.002) were all significant. When stratifying the studies by the pathological variables of heparanase protein expression, this was the case for depth of invasion (1250 patients) (OR=2.76; 95% CI=1.52-5.03; P=0.0009), lymph node metastasis (1178 patients) (OR=4.79 ; 95% CI=3.37-6.80, P<0.00001), tumor size (727 patients) (OR=2.06 ; 95% CI=1.31-3.23; P=0.002) (OR=2.61; 95% CI=2.09-3.27; P=0.000), and TNM stage (1233 patients) (OR=6.85; 95% CI=2.04-23.04; P=0.002). Egger's tests suggested publication bias for depth of invasion, lymph node metastasis, lymph node metastasis and tumor size of heparanase mRNA and protein expression. Conclusions: This meta-analysis suggests that higher heparanase expression in gastric cancer is associated with clinicopathologic features of depth of invasion, lymph node metastasis and TNM stage at mRNA and protein levels, and of tumor size only at the protein level. Egger's tests suggested publication bias for these clinicopathologic features of heparanase mRNA and protein expression, and which may be caused by shortage of relevant studies. As a result, although abundant reports showed heparanase may be associated with clinicopathologic features in gastric cancer, this meta-analysis indicates that more strict studies were needed to evaluate its clinicopathologic significance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.80-88
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• 2008

In this paper, the block cipher algorithms, 3-DES(Triple Data Encryption Standard), AES(Advanced Encryption Standard), SEED, HASH(SHA-1), which are domestic and international standards, have been implemented as an integrated cryptographic engine for smart card applications. For small area and low power design which are essential requirements for portable devices, arithmetic resources are shared for iteration steps in each algorithm, and a two-level clock gating technique was used to reduce the dynamic power consumption. The integrated cryptographic engine was verified with ALTERA Excalbur EPXA10F1020C device, requiring 7,729 LEs(Logic Elements) and 512 Bytes ROM, and its maximum clock speed was 24.83 MHz. When designed by using Samsung 0.18 um STD130 standard cell library, the engine consisted of 44,452 gates and had up to 50 MHz operation clock speed. It was estimated to consume 2.96 mW, 3.03 mW, 2.63 mW, 7.06 mW power at 3-DES, AES, SEED, SHA-1 modes respectively when operating at 25 MHz clock. We found that it has better area-power optimized structure than other existing designs for smart cards and various embedded security systems.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.2 s.302
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• pp.27-36
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• 2005

This thesis proposed an effective encryption method for the DCT-based image/video contents and made it possible to operate in a high speed by implementing it as an optimized hardware. By considering the increase in the amount of the calculation in the image/video compression, reconstruction and encryption, an partial encryption was performed, in which only the important information (DC and DPCM coefficients) were selected as the data to be encrypted. As the result, the encryption cost decreased when all the original image was encrypted. As the encryption algorithm one of the multi-mode AES, DES, or SEED can be used. The proposed encryption method was implemented in software to be experimented with TM-5 for about 1,000 test images. From the result, it was verified that to induce the original image from the encrypted one is not possible. At that situation, the decrease in compression ratio was only $1.6\%$. The hardware encryption system implemented in Verilog-HDL was synthesized to find the gate-level circuit in the SynopsysTM design compiler with the Hynix $0.25{\mu}m$ CMOS Phantom-cell library. Timing simulation was performed by Verilog-XL from CadenceTM, which resulted in the stable operation in the frequency above 100MHz. Accordingly, the proposed encryption method and the implemented hardware are expected to be effectively used as a good solution for the end-to-end security which is considered as one of the important problems.

• Journal of Convergence for Information Technology
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• v.11 no.5
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• pp.30-37
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• 2021

Various devices are connected to the Internet, and attacks using the Internet are occurring. Among such attacks, there are attacks that use malicious URLs to make users access to wrong phishing sites or distribute malicious viruses. Therefore, how to detect such malicious URL attacks is one of the important security issues. Among recent deep learning technologies, neural networks are showing good performance in image recognition, speech recognition, and pattern recognition. This neural network can be applied to research that analyzes and detects patterns of malicious URL characteristics. In this paper, performance analysis according to various parameters was performed on a method of detecting malicious URLs using neural networks. In this paper, malicious URL detection performance was analyzed while changing the activation function, learning rate, and neural network structure. The experimental data was crawled by Alexa top 1 million and Whois to build the data, and the machine learning library used TensorFlow. As a result of the experiment, when the number of layers is 4, the learning rate is 0.005, and the number of nodes in each layer is 100, the accuracy of 97.8% and the f1 score of 92.94% are obtained.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.95-101
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• 2009

Random numbers are used in many sorts of applications. Some applications, like simple software simulation tests, communication protocol verifications, cryptography verification and so forth, need various levels of randomness with various process speeds. In this paper, we propose a fast pseudorandom generator module for embedded systems. The generator module is implemented in hardware which can run in two modes, one of which can generate random numbers with higher randomness but which requires six cycles, the other providing its result within one cycle but with less randomness. An ASIP (Application Specific Instruction set Processor) was designed to implement the proposed pseudorandom generator instruction sets. We designed a processor based on the MIPS architecture,, by using LISA, and have run statistical tests passing the sequence of the Diehard test suite. The HDL models of the processor were generated using CoWare's Processor Designer and synthesized into the Dong-bu 0.18um CMOS cell library using the Synopsys Design Compiler. With the proposed pseudorandom generator module, random number generation performance was 239% faster than software model, but the area increased only 2.0% of the proposed ASIP.

• Journal of the Korean Society for information Management
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• v.24 no.4
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• pp.53-72
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• 2007

This study is designed to assess whether storyboard surrogates are useful enough to be utilized for indexing sources as well as for metadata elements using 12 sample videos and 14 participants. Study shows that first, the match rates of index terms and summaries are significantly different according to video types, which means storyboard surrogates are especially useful for the type of videos of conveying their meanings mainly through images. Second, participants could assign subject keywords and summaries to digital video, sacrificing a little loss of full video clips' match rates. Moreover, the match rate of index terms (0.45) is higher than that of summaries (0.40). This means storyboard surrogates could be more useful for indexing videos rather than summarizing them. The study suggests that 1)storyboard surrogates can be used as sources for indexing and abstracting digital videos; 2) using storyboard surrogates along with other metadata elements (e.g., text-based abstracts) can be more useful for users' relevance judgement; and 3)storyboard surrogates can be utilized as match sources of image-based queries. Finally, in order to improve storyboard surrogates quality, this study proposes future studies: constructing key frame extraction algorithms and designing key frame arrangement models.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.93-98
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• 2004

Serial ATA interface Is inexpensive comparatively and performance is superior. So it is suitable technology in demand that now require data transmission and throughput of high speed. This paper describes a design and implementation of Serial ATA Link layer about error detection and 8b/10b encoder/decoder for DC balance in frequency 150MHz. The 8b/10b Encoder is partitioned into a 5b/6b plus a 3b/4b coder. The logical model of the block is described by using Verilog HDL at register transistor level and the verified HDL is synthesized using standard cell libraries. And it is fabricated with $0.35{\mu}m$ Standard CMOS Cell library and the chip size is about $1500{\mu}m\;*\;1500{\mu}m$. The function of this chip has been verified and tested using testboard with FPGA equipment and IDEC ATS2 test equipment. It is used to frequency of 100MHz in verification processes and supply voltage 3.3V. The result of testing is well on the system clock 100MHz. The designed and verified each blocks may be used IP in the field of high speed serial data communication.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.29-38
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• 2009

In this paper, a high performance pipelined computing design of parallel multiplier-temporal buffer-parallel accumulator is present for the convolution-based non-cascaded architecture aiming at the real time Discrete Wavelet Transform(DWT) processing. The convolved multiplication of DWT would be reduced upto 1/4 by utilizing the filter coefficients symmetry and the up/down sampling; and it could be dealt with 3-5 times faster computation by LUT-based DA multiplication of multiple filter coefficients parallelized for product terms with an image data. Further, the reutilization of computed product terms could be achieved by storing in the temporal buffer, which yields the saving of computation as well as dynamic power by 50%. The convolved product terms of image data and filter coefficients are realigned and stored in the temporal buffer for the accumulated addition. Then, the buffer management of parallel aligned storage is carried out for the high speed sequential retrieval of parallel accumulations. The convolved computation is pipelined with parallel multiplier-temporal buffer-parallel accumulation in which the parallelization of temporal buffer and accumulator is optimize, with respect to the performance of parallel DA multiplier, to improve the pipelining performance. The proposed architecture is back-end designed with 0.18um library, which verifies the 30fps throughput of SVGA(800$\times$600) images at 90MHz.