• 전자공학회논문지D
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• 제35D권4호
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• pp.61-70
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• 1998

The electrical performance of a package is extremely important for high speed digital system operations. CSP(chip scale package) is known to have better electrical performance than the convnetional packages. In this paper, the electrical performance of the BLP(bottom leaded plastic) package, a kind of CSP, has been alayzed by both simulation and real measurement. The electrical perfdormance of a BLP was compared with that of the conventioanl TSOP(thin small outline package). The leadinductanceand lead capacitance were used for the comparison purposes. The new BLP design provides much better electrical performance that TSOP package. It has about 40% favorable parameter values.

• 한국산학기술학회논문지
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• 제13권10호
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• pp.4378-4384
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• 2012

LED 칩 패키징에서 다이 본딩은 웨이퍼에서 분할된 다이를 리드 프레임에 접착제로 고정시켜 칩이 다음 공정을 견딜 수 있는 충분한 강도를 제공하는 중요한 공정이다. 본 논문에서는 PLCC 구조 LED 패키지 프레임에 소형 제너 다이오드를 부착하는 다이 본딩 공정능력의 최적화를 위하여 공정에 영향을 미치는 여러 인자를 분석하여 반응표면분석법을 적용하여 그 결과를 도출하였다. 인자를 분석하여 5인자 3수준 4반응치를 고려하여 실험계획법을 수립하였으며, 그 결과 모든 반응치의 목표를 만족하는 최적 조건을 확보할 수 있었다.

• E2M - 전기 전자와 첨단 소재
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• 제10권6호
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• pp.519-527
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• 1997

The micro crack was occurred where the stress concentrated by the thermal stress which was induced during the cooling period after molding process or by the various reliability tests. In order to estimate the possibility of development from inside micro crack to outside fracture, the fracture toughness of EMC should be measured under the various applicable condition. But study was conducted very rarely for the above area. In order to provide a was to decide the fracture resistance of EMC (Epoxy Molding Compound) of plastic package which is produced by using transfer molding method, measuring fracture is studied. The specimens were made with various EMC material. The diverse combination of test conditions, such as different temperature, temperature /humidity conditions, different filler shapes, and post cure treatment, were tried to examine the effects of environmental condition on the fracture toughness. This study proposed a way which could improve the reliability of LOC(Lead On Chip) type package by comparing the measured $J_{IC}$ of EMC and the calculated J-integral value from FEM(Finite Element Method). The measured $K_{IC}$ value of EMC above glass transition temperature dropped sharply as the temperature increased. The $K_{IC}$ was observed to be higher before the post cure treatment than after the post cure treatment. The change of $J_{IC}$ was significant by time change. J-integral was calculated to have maximum value the angle of the direction of fracture at the lead tip was 0 degree in SOJ package and -30 degree in TSOP package. The results FEM simulation were well agreed with the results of measurement within 5% tolerance. The package crack was proved to be affected more by the structure than by the composing material of package. The structure and the composing material are the variables to reduce the package crack.ack.

• 마이크로전자및패키징학회지
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• 제17권3호
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• pp.17-26
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• 2010

반도체 패키지에 사용되고 있는 유연 솔더는 환경 보호 필요성 대문에 무연 솔더로 빠르게 대체되고 있다. 이와 같은 무연 솔더에 대한 여구는 주로 재료의 발견과 공정 적응성의 관점에서 이루어졌을 뿐, 기계적인 성질이나 신뢰성의 관점에서의 연구는 많이 이루어지지 않았다. 본 논문에서는 무아레 간섭계를 이용하여 유연 솔더와 무연 솔더 실장 WB-PBGA 패키지 결합체의 온도변화에 대한 열-기게적 거동을 해석하였다. 실시간 무아레 간섭계를 이용하여 각 온도 단계에서 변위 분포를 나타내는 간섭무늬를 얻고, 그로부터 유연과 무연의 솔더 조인트를 갖는 WB-PBGA 패키지의 굽힘 변형 거동 및 솔더 볼의 변형률을 비교 분석하였다. 분석결과를 보면 유연 솔더 실장 패키지 결합체의 솔더 볼은 칩경계 부근인 #3 솔더 볼에서 발생하는 전단변형률이 파손에 큰 영향을 미치며, 무연 솔더가 실장된 패키지 결합체의 솔더 볼은 가장 바깥 부근인 #7 솔더 볼에서 발행하는 수직 변형률이 파손에 큰 영향을 미칠 것으로 예측된다, 또한 무연 솔더 실장 패키지 결합체는 같은 온도 조건에서 유연 솔더 실장된 패키지에 비해 굽힘 변형이 휠씬 크게 발생될 뿐 아니라 솔더 볼의 유효변형률도 10% 정도 크게 발생하는 것으로 나타나서 열변형에 의한 파손에 취약할 것으로 예측된다.

• 반도체디스플레이기술학회지
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• 제22권4호
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• pp.124-130
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• 2023

Recently, fan out wafer level packaging, which enables high integration, miniaturization, and low cost, is being rapidly applied in the semiconductor industry. In particular, FOWLP is attracting attention in the mobile and Internet of Things fields, and is recognized as a core technology that will lead to technological advancements such as 5G, self-driving cars, and artificial intelligence in the future. However, as chip density and package size within the package increase, FOWLP warpage is emerging as a major problem. These problems have a direct impact on the reliability and electrical performance of semiconductor products, and in particular, cause defects such as vacuum leakage in the manufacturing process or lack of focus in the photolithography process, so technical demands for solving them are increasing. In this paper, warpage simulation according to the thickness of FOWLP material was performed using finite element analysis. The thickness range was based on the history of similar packages, and as a factor causing warpage, the curing temperature of the materials undergoing the curing process was applied and the difference in deformation due to the difference in thermal expansion coefficient between materials was used. At this time, the stacking order was reflected to reproduce warpage behavior similar to reality. After performing finite element analysis, the influence of each variable on causing warpage was defined, and based on this, it was confirmed that warpage was controlled as intended through design modifications.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 추계 기술심포지움
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• pp.111-114
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• 2001

Optical transmitter and receiver are the essential components for optical communication. For these components, butterfly type packages are used which are comprised of metal housing, multilayer ceramic inserts, lead and window. In this study, 2.5 Gbps DFB(Distributed -Feedback) LD(Laser Diode) package was fabricated and characterized. Metal housing showed good thermal conductivity (200W/mK) and well matched TCE(6.7ppm/K) with GaAs chip. Ceramic inserts also showed good VSWR(Voltage Standing Wave Ratio) characteristics(<2.0). By brazing technology, all the elements were combined and sealed. RF characteristics of the package mounted on the PWB was also tested.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2006년도 춘계 학술대회 개요집
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• pp.218-220
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• 2006

Sn-3.0Ag-0.5Cu solder is widely used as micro-joining materials of flip chip package(FCP) because of the fact that it causes less dissolution and has good thermal fatigue property. However, compared with ternary electroplating in the manufacturing process, binary electroplating is still used in industrial field because of easy to make plating solution and composition control. The objective of this research is to fabricate Sn-3.0Ag-0.5Cu solder bumping having accurate composition. The ternary Sn-3.0Ag-0.5Cu solder bumping could be made on a Cu pad by sequent binary electroplating of Sn-Cu and Sn-Ag. Composition of the solder was estimated by EDS and ICP-OES. The thickness of the bump was measured using SEM and the microstructure of intermetallic-compounds(IMCs) was observed by SEM and EDS. From the results, contents of Ag and CU found to be at $2.7{\pm}0.3wt%\;and\;0.4{\pm}0.1wt%$, respectively.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2004년도 ISMP Pb-free solders and the PCB technologies related to Pb-free solders
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• pp.233-241
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• 2004

A new alloy definition will be presented concerning increasing demands for the board level reliability of miniaturized interconnections. The damage mechanism for LFBGA components on different board finishes is not quite understood. Further demands from mobile phones are the drop test, characterizing interface performance of different package constructions in relation to decreased pad constructions and therefore interfaces. The paper discusses the characterization of interfaces based on SnPb, SnPbXYZ, SnAgCu and SnAgCuInNd ball materials and SnAgCuInNd as solder paste, the stability after accelerated tests and the description of modified interfaces strictly related to the assembly conditions, dissolution behavior of finishes on board side and the influence of intermetallic formation. The type of intermetallic as well as the quantity of intermetallics are observed, primaliry the hardness, E modules describing the ability of strain/stress compensation. First results of board level reliability are presented after TCT-40/+150. Improvement steps from the ball formulation will be discussed in conjunction to the implementation of lead free materials In order to optimize ball materials for area array devices accelareted aging conditions like TCTs were used to analyze the board level reliability of different ball materials for BGA, LFBGA, CSP, Flip Chip. The paper outlines lead-free ball analysis in comparison to conventional solder balls for BGA and chip size packages. The important points of interest are the description of processability related to existing ball attach procedures, requirements of interconnection properties and the knowledge gained the board level reliability. Both are the primary acceptance criteria for implementation. Knowledge about melting characteristic, surface tension depend on temperature and organic vehicles, wetting behavior, electrical conductivity, thermal conductivity, specific heat, mechanical strength, creep and relaxation properties, interactions to preferred finishes (minor impurities), intermetallic growth, content of IMC, brittleness depend on solved elements/IMC, fatigue resistance, damage mechanism, affinity against oxygen, reduction potential, decontamination efforts, endo-/exothermic reactions, diffusion properties related to finishes or bare materials, isothermal fatigue, thermo-cyclic fatigue, corrosion properties, lifetime prediction based on board level results, compatibility with rework/repair solders, rework temperatures of modified solders (Impurities, change in the melting point or range), compatibility to components and laminates.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2004년도 ISMP Pb-free solders and the PCB technologies related to Pb-free solders
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• pp.211-219
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• 2004

A new alloy definition will be presented concerning increasing demands for the board level reliability of miniaturized interconnections. The damage mechanism for LFBGA components on different board finishes is not quite understood. Further demands from mobile phones are the drop test, characterizing interface performance of different package constructions in relation to decreased pad constructions and therefore interfaces. The paper discusses the characterization of interfaces based on SnPb, SnPbXYZ, SnAgCu and SnAgCuInNd ball materials and SnAgCuInNd as solder paste, the stability after accelerated tests and the description of modified interfaces stric시y related to the assembly conditions, dissolution behavior of finishes on board side and the influence of intermetallic formation. The type of intermetallic as well as the quantity of intermetallics are observed, primaliry the hardness, E modules describing the ability of strain/stress compensation. First results of board level reliability are presented after TCT-40/+150. Improvement steps from the ball formulation will be discussed in conjunction to the implementation of lead free materials. In order to optimize ball materials for area array devices accelareted aging conditions like TCTs were used to analyze the board level reliability of different ball materials for BGA, LFBGA, CSP, Flip Chip. The paper outlines lead-free ball analysis in comparison to conventional solder balls for BGA and chip size packages. The important points of interest are the description of processability related to existing ball attach procedures, requirements of interconnection properties and the knowledge gained the board level reliability. Both are the primary acceptance criteria for implementation. Knowledge about melting characteristic, surface tension depend on temperature and organic vehicles, wetting behavior, electrical conductivity, thermal conductivity, specific heat, mechanical strength, creep and relaxation properties, interactions to preferred finishes (minor impurities), intermetallic growth, content of IMC, brittleness depend on solved elements/IMC, fatigue resistance, damage mechanism, affinity against oxygen, reduction potential, decontamination efforts, endo-/exothermic reactions, diffusion properties related to finishes or bare materials, isothermal fatigue, thermo-cyclic fatigue, corrosion properties, lifetime prediction based on board level results, compatibility with rework/repair solders, rework temperatures of modified solders (Impurities, change in the melting point or range), compatibility to components and laminates.

• 마이크로전자및패키징학회지
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• 제16권4호
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• pp.1-4
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• 2009

본 연구에서는 실리콘 웨이퍼에 2중 다이싱 공정의 적용이 리드-온-칩 패키지로 조립되는 반도체 디바이스의 T.C. ($-65^{\circ}C$에서 $150^{\circ}C$까지의 온도변화에 지배되는 신뢰성 실험) 신뢰성에 어떠한 영향을 미치는 지를 보여준다. 기존 싱글 다이싱 공정은 웨이퍼에서 분리된 디바이스의 테두리 부위가 다이싱으로 인해 기계적으로 손상되는 결과를 보였으나, 2중 다이싱 공정은 분리된 디바이스의 테두리 부위가 거의 손상되지 않고 보존되는 것을 확인할 수 있었다. 이는 2중 다이싱의 경우 다이싱 동안 웨이퍼의 전면에 도입된 노치부위가 선택적으로 파손되면서 분리된 디바이스의 테두리 부위를 보호하기 때문으로 해석된다. 온도변화 실험을 통해 2중 다이싱 공정의 도입이 단일 다이싱 공정에 비해 T.C. 신뢰성에서도 대단히 좋은 결과를 보인다는 것을 확인할 수 있었다.