• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.36 no.4A
• /
• pp.414-422
• /
• 2011

This paper describes a design of low-density parity-check(LDPC) decoder supporting block length 2,304-bit and code rate 1/2 of IEEE 802.16e mobile WiMAX standard. The designed LDPC decoder employs the min-sum algorithm and partially parallel layered-decoding architecture which processes a sub-matrix of $96{\times}96$ in parallel. By exploiting the properties of the min-sum algorithm, a new memory reduction technique is proposed, which reduces check node memory by 46% compared to conventional method. Functional verification results show that it has average bit-error-rate(BER) of $4.34{\times}10^{-5}$ for AWGN channel with Fb/No=2.1dB. Our LDPC decoder synthesized with a $0.18{\mu}m$ CMOS cell library has 174,181 gates and 52,992 bits memory, and the estimated throughput is about 417 Mbps at 100-MHz@l.8-V.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.44 no.3
• /
• pp.68-73
• /
• 2007

Recently, WSN(wireless sensor networks) consists of several sensor nodes in sensor field. And each sensors have the enforced energy constraint. Therefore, it is important to manage energy efficiently. In WSN application system, FEC(Forward error correction) increases the energy efficiency and data reliability of the data transmission. LDPC(Low density parity check) code is one of the FEC code. It needs more encoding operation than other FEC code by growing codeword length. But this code can approach the Shannon capacity limit and it is also can be used to increase the data reliability and decrease the transmission energy. In this paper, the author adopt Linear-Congruence method at generating parity check matrix of LDPC(Low density parity check) codes to reduce the complexity of encoding process and to enhance the energy efficiency in the WSN. As a result, the proposed algorithm can increase the encoding energy efficiency and the data reliability.

• Transactions of the Society of Information Storage Systems
• /
• v.3 no.3
• /
• pp.126-128
• /
• 2007

일반적으로 주어진 하나의 H matrix 로 다수의 코드율을 가지는 코드화가 가능하다. 하지만 Low Density Parity Check(LDPC) 코드의 H matrix는 H matrix 내의 1의 개수와 위치에 따라 그 성능이 달라짐으로 해서 하나의 H matrix로 다수의 코드율을 대응하기 위한 설계 방법이 요구된다. H matrix 의 성능은 일반적으로 girth나 minimum distance에 의해 좌우되고 H matrix의 1의 위치에 따라 달라진다. 본 논문에서는 H matrix의 girth 와 minimum distance에 입각한 다수 개의 코드율이 대응 가능한 LDPC code의 H matrix 설계 방법을 제시하고자 한다. 이렇게 함으로써 하나의 H matrix로 다수의 코드율에 따른 각각의 성능을 일정 수준 이상 유지하는 multi-rate LDPC code가 가능하다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.5A
• /
• pp.402-406
• /
• 2005

A multiple input multiple output orthogonal frequency division multiplexing (MIMO-OFDM) system using low-density parity-check (LDPC) code and iterative decoding is presented. The iterative decoding is performed by combining the zero-forcing technique and LDPC decoding through the use of the 'turbo principle.' The proposed system is shown to be effective with high order modulation and outperforms the space frequency block code (SFBC) method with iterative decoding.

• Journal of electromagnetic engineering and science
• /
• v.4 no.1
• /
• pp.17-22
• /
• 2004

In this paper, we implement an efficient MLC/PDL system for AWGN channels. In terms of the tradeoff between the hardware implementation and system performance, proposed algebra LDPC codes are optimized by the Gaussian approximation(GA) according to the rate of each level assigned by the capacity rule and chosen as the component code. System performance with Ungerboeck Partitioning(UP), Miked Partitioning(MP) and Gray Mapping(GM) of 8PSK are evaluated, respectively. Many results are presented in this paper; they can indicate that the proposed MLC/PDL system using optimized algebra LDPC codes with different code rate, capacity rule and Gray mapping(GM) can achieve the best performance.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.10 no.6
• /
• pp.2648-2668
• /
• 2016

Modern mobile devices are equipped with various accelerated processing units to handle computationally intensive applications; therefore, Open Computing Language (OpenCL) has been proposed to fully take advantage of the computational power in heterogeneous systems. This article introduces a parallel software decoder of Low Density Parity Check (LDPC) codes on an embedded heterogeneous platform using an OpenCL framework. The LDPC code is one of the most popular and strongest error correcting codes for mobile communication systems. Each step of LDPC decoding has different parallelization characteristics. In the proposed LDPC decoder, steps suitable for task-level parallelization are executed on the multi-core central processing unit (CPU), and steps suitable for data-level parallelization are processed by the graphics processing unit (GPU). To improve the performance of OpenCL kernels for LDPC decoding operations, explicit thread scheduling, vectorization, and effective data transfer techniques are applied. The proposed LDPC decoder achieves high performance and high power efficiency by using heterogeneous multi-core processors on a unified computing framework.

• ETRI Journal
• /
• v.45 no.3
• /
• pp.404-417
• /
• 2023

This paper proposed a novel method for constructing quasi-cyclic low-density parity-check (QC-LDPC) codes of medium to high code rates that can be applied in cloud data storage systems, requiring better error correction capabilities. The novelty of this method lies in the construction of sparse base matrices, using a girth greater than 4 that can then be expanded with a lift factor to produce high code rate QC-LDPC codes. Investigations revealed that the proposed large-sized QC-LDPC codes with high code rates displayed low encoding complexities and provided a low bit error rate (BER) of 10^-10 at 3.5 dB E_b/N₀ than conventional LDPC codes, which showed a BER of 10^-7 at 3 dB E_b/N₀. Subsequently, implementation of the proposed QC-LDPC code in a softwaredefined radio, using the NI USRP 2920 hardware platform, was conducted. As a result, a BER of 10^-6 at 4.2 dB E_b/N₀ was achieved. Then, the performance of the proposed codes based on their encoding-decoding speeds and storage overhead was investigated when applied to a cloud data storage (GCP). Our results revealed that the proposed codes required much less time for encoding and decoding (of data files having a 10 MB size) and produced less storage overhead than the conventional LDPC and Reed-Solomon codes.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.7 no.2
• /
• pp.317-325
• /
• 2012

In this paper, we consider the encoding scheme of Low Density Parity Check codes. In particular, using the Jacket Pattern and circulant permutation matrices, we propose the simple encoding scheme of Richardson's lower triangular matrix. These encoding scheme can be extended to a flexible code rate. Based on the simple matrix process, also we can design low complex and simple encoders for the flexible code rates.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.49 no.4
• /
• pp.335-342
• /
• 2021

By using HLS when developing a communication system FPGA, HDL code can be automatically generated from a little modified C/C++ source code used for performance verification, which has the advantage of shortening the development period. In this paper, a method of designing a telemetry standard 106-17 LDPC decoder in C language is proposed using Xilinx's Vivado HLS, and by synthesizing Spartan-7 and Kintex-7 as target devices, throughput and FPGA utilization rate was compared.

• 전자공학회논문지 IE
• /
• v.43 no.4
• /
• pp.115-121
• /
• 2006

In this paper, we proposed about data error check and correction on channel transmission in the communication system. LDPC codes are used for minimizing channel errors by modeling AWGN Channel as a VDSL system. Because LDPC Codes use low density parity bit, mathematical complexity is low and relating processing time becomes shorten. Also the performance of LDPC code is better than that of turbo code in long code word on iterative decoding algorithm. This algorithm is better than conventional algorithms to correct errors, the proposed algorithm assigns weights for errors concerning parity bits. The proposed weighted Bit-flipping algorithm is better than the conventional Bit-flipping algorithm and we are recognized improve gain rate of 1 dB.