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http://dx.doi.org/10.3837/tiis.2016.06.011

Parallel LDPC Decoding on a Heterogeneous Platform using OpenCL  

Hong, Jung-Hyun (Department of Electronics and Computer Engineering, Hanyang University)
Park, Joo-Yul (Department of Electronic Engineering, Hanyang University)
Chung, Ki-Seok (Department of Electronic Engineering, Hanyang University)
Publication Information
KSII Transactions on Internet and Information Systems (TIIS) / v.10, no.6, 2016 , pp. 2648-2668 More about this Journal
Abstract
Modern mobile devices are equipped with various accelerated processing units to handle computationally intensive applications; therefore, Open Computing Language (OpenCL) has been proposed to fully take advantage of the computational power in heterogeneous systems. This article introduces a parallel software decoder of Low Density Parity Check (LDPC) codes on an embedded heterogeneous platform using an OpenCL framework. The LDPC code is one of the most popular and strongest error correcting codes for mobile communication systems. Each step of LDPC decoding has different parallelization characteristics. In the proposed LDPC decoder, steps suitable for task-level parallelization are executed on the multi-core central processing unit (CPU), and steps suitable for data-level parallelization are processed by the graphics processing unit (GPU). To improve the performance of OpenCL kernels for LDPC decoding operations, explicit thread scheduling, vectorization, and effective data transfer techniques are applied. The proposed LDPC decoder achieves high performance and high power efficiency by using heterogeneous multi-core processors on a unified computing framework.
Keywords
Error correcting code; LDPC decoder; parallel processing; heterogeneous computing; OpenCL;
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Times Cited By KSCI : 2  (Citation Analysis)
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1 J.-H. Hong, Y.-H. Ahn, B.-J. Kim, and K.-S. Chung, “Design of OpenCL Framework for Embedded Multi-core Processors,” IEEE Trans. Consumer Electron., vol. 60, no. 2, pp. 233-241, May, 2014. Article (CrossRef Link).   DOI
2 Khronos OpenCL Working Group, The OpenCL Specification Version 1.2, Document Revision 19, 2012. Article (CrossRef Link).
3 R.G. Gallager, “Low-density parity check codes,” IRE Trans. Information Theory, vol. 8, no. 1, pp. 21-28, Jan. 1962. Article (CrossRef Link).   DOI
4 E.-S. Jeon et al., "Iterative detection and ICI cancellation for MISO-mode DVB-T2 system with dual carrier frequency offsets," KSII Transactions on Internet and Information Systems, vol. 6, no. 2, pp. 702-721, Feb. 2012. Article (CrossRef Link).   DOI
5 K. Zhang, X. Huang, and Z. Wang, “A Dual-Rate LDPC Decoder for China Multimedia Mobile Broadcasting Systems,” IEEE Trans. Consumer Electron., vol. 56, no. 2, pp. 399-407, May, 2010. Article (CrossRef Link).   DOI
6 G. Wang, M. Wu, B. Yin, and J. R. Cavallaro, "High throughput low latency LDPC decoding on GPU for SDR systems," in Proc. of 2013 IEEE Global Conference on Signal Processing, pp.1258-1261, Dec. 2013. Article (CrossRef Link).
7 S. Wang, S. Cheng, and Q. Wu, "A parallel decoding algorithm of LDPC codes using CUDA," in Proc. of 2008 42nd Asilomar Conference on Signals, Systems and Computers, pp. 171-175, Oct. 2008. Article (CrossRef Link).
8 B. Gal and C. Jego, “High-throughput LDPC decoder on low-power embedded processors,” IEEE Communication Letters, vol. 1, no. 99, pp. 1-4, Sep. 2015. Article (CrossRef Link).
9 G. Falcão, V. Silva , L. Sousa, and J. Andrade, “Portable LDPC decoding on multicores using OpenCL,” IEEE Signal Processing Magazine, vol. 29, no. 4, pp. 81-109, July, 2012. Article (CrossRef Link).   DOI
10 J.-Y. Park and K.-S. Chung, “Parallel LDPC decoding using CUDA and OpenMP,” EURASIP Journal on Wireless Communications and Networking, vol. 2011, no. 1, Dec. 2011. Article (CrossRef Link).
11 D. Leonardo and R. Menon, “OpenMP: an industry standard API for shared-memory programming,” IEEE Computational Science & Engineering, vol. 5, no.1, pp. 46-55, Jan. 1998. Article (CrossRef Link).   DOI
12 J.-H. Hong, W.-J. Kim, and K.-S. Chung, “A Parallelization Technique with Integrated Multi-Threading for Video Decoding on Multi-core Systems,” KSII Transactions on Internet and Information Systems, vol. 7, no. 10, pp. 2479-2496, Oct. 2013. Article (CrossRef Link).   DOI
13 B. R. Gaster, L. Howes, D. R. Kaeli, P. Mistry, and D. Schadd, Heterogeneous computing with OpenCL: Revised OpenCL 1.2 Edition, Morgan Kaufmann, 2012. Article (CrossRef Link).
14 J. Shen, J. Fang, H. Sips, and A. L. Varbanescu, "Performance Traps in OpenCL for CPUs," in Proc. of 21st Euro Micro International Conference on Parallel, Distributed, and Network-Based Processing, pp. 38-45, Feb. 2013. Article (CrossRef Link).
15 K. Gunnam, G. Choi, W. Wang, and M. Yeary, "Multi-Rate Layered Decoder Architecture for Block LDPC Codes of the IEEE 802.11n Wireless Standard," in Proc. of 2007 IEEE International Symposium on Circuits and Systems, pp. 1645-1648, May, 2007. Article (CrossRef Link).
16 Intel Corporation, Intel Cilk Plus Language Specification, Document Revision 1.0, 2010. Article (CrossRef Link).
17 G. Sheng, Z. Yong, S. Zhukai, and S. Fan, "Optimize power for portable games on Ultrabook," in Proc. of 2012 IEEE International Conference on Energy Aware Computing, pp. 1-6, Dec. 2012. Article (CrossRef Link).
18 J. Li, J. Ma, and G. He, “A memory efficient parallel layered QC-LDPC decoder for CMMB systems,” Integration, the VLSI Journal, vol. 46, no. 4, pp. 359-368, Sep. 2013. Article (CrossRef Link).   DOI