• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.9
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• pp.746-752
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• 2012

SVC layered video is consists of a Base Layer (BL) and Enhancement Layer (EL). Without the base layer decoding, the higher EL layer can not be decoded. Therefore, successful transfer of the BL is important factor for improving the SVC video data. In this paper, we propose a network coding of layered video to improve success decoding probability with the importance order of the video data over a multi-relay system. We shows that formula analysis and experimental results of the proposed network coding scheme. In addition, we shows performance of video quality according to the number of relays.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.798-801
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• 2010

This paper describes an efficient architecture for LDPC(Low-Density Parity Check) decoder, which supports three block lengths (648, 1,296, 1,944) of IEEE 802.11n standard. To minimize hardware complexity, the min-sum algorithm and block-serial layered structure are adopted in DFU(Decoding Function Unit) which is a main functional block in LDPC decoder. The optimized H-ROM structure for multi block lengths reduces the ROM size by 42% as compared to the conventional method. Also, pipelined memory read/write scheme for inter-layer DFU operations is proposed for an optimized operation of LDPC decoder.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.4
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• pp.79-89
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• 2010

Recently, distributed video coding (DVC) has been actively studied for low complexity video encoder. The complexity of the encoder in DVC is much simpler than that of traditional video coding schemes such as H.264/AVC, but the complexity of the decoder in DVC increases. In this paper, we propose the Region-Of-Interest (ROI) based DVC with low decoding complexity. The proposed scheme uses the ROI, the region the motion of objects is quickly moving as the input of the Wyner-Ziv (WZ) encoder instead of the whole WZ frame. In this case, the complexity of encoder and decoder is reduced, and the bite rate decreases. Experimental results show that the proposed scheme obtain 0.95 dB as the maximum PSNR gain in Hall Monitor sequence and 1.87 dB in Salesman sequence. Moreover, the complexity of encoder and decoder in the proposed scheme is significantly reduced by 73.7% and 63.3% over the traditional DVC scheme, respectively. In addition, we employ the layered belief propagation (LBP) algorithm whose decoding convergence speed is 1.73 times faster than belief propagation algorithm as the Low-Density Parity-Check (LDPC) decoder for low decoding complexity.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2008.11a
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• pp.181-184
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• 2008

The paper describes a Layered Modulation using the SVC signals and studies the properties of the modulation with respect to several parameters by the computer simulation. The SVC signals will include a base layer signal and an enhancement signal, and the base layer signal is the more important one in its channel robustness. The parameters will include a carrier frequency, a bandwidth, power level, modulation type and code rate. We analyze the demodulating and decoding process of the Layered Modulation system through several scatter plots. And then we discuss the affect of the layer signal power difference to the BER performance, which also proves the base layer signal is more important than the enhancement layer signal.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.5A
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• pp.487-493
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• 2008

In this paper, we consider coded layered space-time architecture in MIMO-OFDM channels. Vertical Bell Lab Layered Space-Time(V-BLAST) scheme employing ordered successive interference cancellation(OSIC) algorithm provides very high spectral efficiency with low computational complexity. However, the error propagation is a major drawback constraining the overall performance of the V-BLAST system significantly. Based on this problem, we derive an improved detector using soft bit log-likelihood ratio(LLR) value. Simulation results show that the proposed detector outperforms the conventional V-BLAST scheme under spatially uncorrelated as well as correlated fading channels.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.6
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• pp.1355-1362
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. Our LDPC decoder adopts a block-serial architecture based on min-sum algorithm and layered decoding scheme. A novel way to store check-node values and parity check matrix reduces the sizes of check-node memory and H-ROM. An efficient scheme for check-node memory addressing is used to achieve stall-free read/write operations. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.722-725
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• 2010

In this paper, BER performance and error convergence speed of layered LDPC(Low Density Parity Check) decoder which supports IEEE 802.16e WiMAX standard is analyzed, and optimal design conditions for hardware implementation are derived. A LDPC decoder is modeled and simulated at AWGN channel with QPSK modulation by Matlab. The parity check matrix(PCM) for IEEE 802.16e standard which has block lengths of 576, 1440, 2304 and code rates of 1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6 are used. Fixed-point simulation results show that fixed-point bit-width should be more than 8 bits for acceptable decoding performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.4A
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• pp.414-422
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• 2011

This paper describes a design of low-density parity-check(LDPC) decoder supporting block length 2,304-bit and code rate 1/2 of IEEE 802.16e mobile WiMAX standard. The designed LDPC decoder employs the min-sum algorithm and partially parallel layered-decoding architecture which processes a sub-matrix of $96{\times}96$ in parallel. By exploiting the properties of the min-sum algorithm, a new memory reduction technique is proposed, which reduces check node memory by 46% compared to conventional method. Functional verification results show that it has average bit-error-rate(BER) of $4.34{\times}10^{-5}$ for AWGN channel with Fb/No=2.1dB. Our LDPC decoder synthesized with a $0.18{\mu}m$ CMOS cell library has 174,181 gates and 52,992 bits memory, and the estimated throughput is about 417 Mbps at 100-MHz@l.8-V.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.3 s.333
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• pp.15-18
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• 2005

Multiple space-time codes (M-STTC) is composed of several space-time codes. That provides high transmission rate as well as diversity and coding gain without bandwidth expansion. In this paper, the layered receiver structures employing whitening process for M-STTC is proposed. The proposed receiver is composed of the decoding order decision block and the layered detection block. The whitening process in the latter is utilized to maximize the receive diversity gain in the layered detection. The layered receiver employing whitening process has more diversity gain and advantage of the required number of receive antenna over the layered detection with MMSE nulling. The proposed scheme achieves a 5dB gain compared to the coded layered space-time processing at the FER of $10^{-2}$.

• Journal of Satellite, Information and Communications
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• v.6 no.2
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• pp.78-83
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• 2011

In this paper, we propose a computationally efficient early stopping method to reduce the average number of iterations. The conventional early stopping methods have too much computational complexity to compute the stopping criterion. Thus, only the hard decision based early stopping method is suitable to realize the hardware of LDPC decoder. However, this method also can increase the computational complexity of LDPC decoder. The proposed method can effectively reduce the computational complexity of stopping criterion as we do not compute hard decision, and we combine the stopping criterion with horizontal shuffling scheduling decoding scheme. The simulation results show that a new early stopping method achieves acceptable bit error rate performance also reduces the average number of iterations.