• Title/Summary/Keyword: layer doping

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Growth and characterization of GaAs and AlGaAs with MBE growth temperature (MBE 성장온도에 따른 GaAs 및 AlGaAs의 전기광학적 특성)

  • Seung Woong Lee;Hoon Young Cho;Eun Kyu Kim;Suk-Ki Min;Jung Ho Park
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.4 no.1
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    • pp.11-20
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    • 1994
  • GaAs and AlGaAs epi-layers were grown on semi-insulating (100) GaAs substrate by molecular beam epitaxy (MBE) and their electrical and optical properties have been investigated by several measurements. In undoped GaAs, the p-type GaAs layers with the good surface morphology were obtained under the growth conditions of the substrate temperatures ranging from 570 to $585^{\circ}C$ and the $As_4$/Ga ratios from 17 to 22. In the samples with the growth rates of the ranges of $0.9~1.1 {\mu}m/h$, the impurity concentrations were in the ranges of $1.5{\times}10^{14}~5.6{\times}10^{14}cm^{-3}$ with the Hall mobilities of $590~410cm^2/V-s$. In the Si-doped GaAs, the n-type GaAs layers with low electro trap, only two hole deep levels were observed with uniform doping profiles (<1%). AlGaAs layers with good surface morphology and crystallinity were grown under an optimum condition of the substrate temperature, $600^{\circ}C $. 8 deep level defects were observed between 0.17~0.85eV in undoped AlGaAs layers.

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Luminescence Characteristics of Mg2+·Ba2+ Co-Doped Sr2SiO4:Eu Yellow Phosphor for Light Emitting Diodes (LED용Mg2+·Ba2+Co-Doped Sr2SiO4:Eu 노란색 형광체의 발광특성)

  • Choi, Kyoung-Jae;Jee, Soon-Duk;Kim, Chang-Hae;Lee, Sang-Hyuk;Kim, Ho-Kun
    • Journal of the Korean Ceramic Society
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    • v.44 no.3 s.298
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    • pp.147-151
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    • 2007
  • An improvement for the efficiency of the $Sr_{2}SiO_{4}:Eu$ yellow phosphor under the $450{\sim}470\;nm$ excitation range have been achieved by adding the co-doping element ($Mg^{2+}\;and\;Ba^{2+}$) in the host. White LEDs were fabricated through an integration of an blue (InGaN) chip (${\lambda}_{cm}=450\;nm$) and a blend of two phosphors ($Mg^{2+},\;Ba^{2+}\;co-doped\;Sr_{2}SiO_{4}:Eu$ yellow phosphor+CaS:Eu red phosphor) in a single package. The InGaN-based two phosphor blends ($Mg^{2+},\;Ba^{2+}\;co-doped\;Sr_{2}SiO_{4}:Eu$ yellow phosphor+CaS:Eu red phosphor) LEDs showed three bands at 450 nm, 550 nm and 640 nm, respectively. The 450 nm emission band was due to a radiative recombination from an InGaN active layer. This 450 nm emission was used as an optical transition of the $Mg^{2+},\;Ba^{2+}\;co-doped\;Sr_{2}SiO_{4}:Eu$ yellow phosphor+CaS:Eu red phosphor. As a consequence of a preparation of white LEDs using the $Mg^{2+},\;Ba^{2+}\;co-doped\;Sr_{2}SiO_{4}:Eu$ yellow phosphor+CaS:Eu red phosphor yellow phosphor and CaS:Eu red phosphor, the highest luminescence efficiency was obtained at the 0.03 mol $Ba^{2+}$ concentration. At this time, the white LEDs showed the CCT (5300 K), CRI (89.9) and luminous efficacy (17.34 lm/W).

Physical Characterization of GaAs/$\textrm{Al}_{x}\textrm{Ga}_{1-x}\textrm{As}$/GaAs Heterostructures by Deep Level transient Spectroscopy (DLTS 방법에 의한 GaAs/$\textrm{Al}_{x}\textrm{Ga}_{1-x}\textrm{As}$/GaAs 이종구조의 물성분석에 관한 연구)

  • Lee, Won-Seop;Choe, Gwang-Su
    • Korean Journal of Materials Research
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    • v.9 no.5
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    • pp.460-466
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    • 1999
  • The deep level electron traps in AP-MOCVD GaAs/undoped Al\ulcornerGa\ulcornerAs/n-type GaAs heterostructures have been investigated by means of Deep Level Transient Spectroscopy DLTS). In terms of the experimental procedure, GaAs/undoped Al\ulcornerGa\ulcornerAs/n-type GaAs heterostructures were deposited on 2" undoped semi-insulating GaAs wafers by the AP-MOCVD method at $650^{\circ}C$ with TMGa, AsH3, TMAl, and SiH4 gases. The n-type GaAs conduction layers were doped with Si to the target concentration of about 2$\times$10\ulcornercm\ulcorner. The Al content was targeted to x=0.5 and the thicknesses of Al\ulcornerGa\ulcornerAs layers were targeted from 0 to 40 nm. In order to investigate the electrical characteristics, an array of Schottky diodes was built on the heterostructures by the lift-off process and Al thermal evaporation. Among the key results of this experiment, the deep level electron traps at 0.742~0.777 eV and 0.359~0.680 eV were observed in the heterostructures; however, only a 0.787 eV level was detected in n-type GaAs samples without the Al\ulcornerGa\ulcornerAs overlayer. It may be concluded that the 0.787 eV level is an EL2 level and that the 0.742~0.777 eV levels are related to EL2 and residual oxygen impurities which are usually found in MOCVD GaAs and Al\ulcornerGa\ulcornerAs materials grown at $630~660^{\circ}C$. The 0.359~0.680 eV levels may be due to the defects related with the al-O complex and residual Si impurities which are also usually known to exist in the MOCVD materials. Particularly, as the Si doping concentration in the n-type GaAs layer increased, the electron trap concentrations in the heterostructure materials and the magnitude of the C-V hysteresis in the Schottky diodes also increased, indicating that all are intimately related.ated.

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a-Si:H/c-Si Heterojunction Solar Cell Performances Using 50 ㎛ Thin Wafer Substrate (50 ㎛ 기판을 이용한 a-Si:H/c-Si 이종접합 태양전지 제조 및 특성 분석)

  • Song, Jun Yong;Choi, Jang Hoon;Jeong, Dae Young;Song, Hee-Eun;Kim, Donghwan;Lee, Jeong Chul
    • Korean Journal of Materials Research
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    • v.23 no.1
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    • pp.35-40
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    • 2013
  • In this study, the influence on the surface passivation properties of crystalline silicon according to silicon wafer thickness, and the correlation with a-Si:H/c-Si heterojunction solar cell performances were investigated. The wafers passivated by p(n)-doped a-Si:H layers show poor passivation properties because of the doping elements, such as boron(B) and phosphorous(P), which result in a low minority carrier lifetime (MCLT). A decrease in open circuit voltage ($V_{oc}$) was observed when the wafer thickness was thinned from $170{\mu}m$ to $50{\mu}m$. On the other hand, wafers incorporating intrinsic (i) a-Si:H as a passivation layer showed high quality passivation of a-Si:H/c-Si. The implied $V_{oc}$ of the ITO/p a-Si:H/i a-Si:H/n c-Si wafer/i a-Si:H/n a-Si:H/ITO stacked layers was 0.715 V for $50{\mu}m$ c-Si substrate, and 0.704 V for $170{\mu}m$ c-Si. The $V_{oc}$ in the heterojunction solar cells increased with decreases in the substrate thickness. The high quality passivation property on the c-Si led to an increasing of $V_{oc}$ in the thinner wafer. Short circuit current decreased as the substrate became thinner because of the low optical absorption for long wavelength light. In this paper, we show that high quality passivation of c-Si plays a role in heterojunction solar cells and is important in the development of thinner wafer technology.

Preparation of pseudo n-type Polyaniline and Evaluation of Electrochemical Properties (가상 n형 폴리아닐린의 제조 및 전기화학적 특성평가)

  • 김래현;최선용;정건용
    • Membrane Journal
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    • v.13 no.3
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    • pp.162-173
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    • 2003
  • The pseudo n-type polyaniline was prepared by doping of camphorsulfonic acid(CSA) and dodecylbenzenesulfonic acid(DBSA) as the dopants in solvent of N-methyl-2-pyrrolidinone(NMP). The dopants in polymer structure was qualitatively analyzed using FT-IR. The influence on electrochemical properties with dopant concentration of PANI film were investigated. The electrochemical characteristics of the n-type PANI electrode that coated on ITO were evaluated by cyclic voltammetry(CV) and AC impedance method. The prepared PANI were confirmed as n-type PANI from FT-IR and CV. The charge transfer resistance of film on PANI/CSA electrode were measured as 1.14{\sim}1.09k{\mu}$by AC impedance. The charge transfer resistance of PANI/DBSA electrode decreased with increasing the mole ratio of DBSA as 27.73{\sim}8.37 k{\mu}$. The double layer capacitance of PANI/CSA electrode was showed almost constant value as $13.47{\sim}14.59 {\mu}F$ and that of PANI/DBSA electrode increased with increasing mole ratio of DBSA from 0.49 to $1.20 {\mu}F$.

Simulation Study of a Large Area CMOS Image Sensor for X-ray DR Detector with Separate ROICs (센서-회로 분리형 엑스선 DR 검출기를 위한 대면적 CMOS 영상센서 모사 연구)

  • Kim, Myung Soo;Kim, Hyoungtak;Kang, Dong-uk;Yoo, Hyun Jun;Cho, Minsik;Lee, Dae Hee;Bae, Jun Hyung;Kim, Jongyul;Kim, Hyunduk;Cho, Gyuseong
    • Journal of Radiation Industry
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    • v.6 no.1
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    • pp.31-40
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    • 2012
  • There are two methods to fabricate the readout electronic to a large-area CMOS image sensor (LACIS). One is to design and manufacture the sensor part and signal processing electronics in a single chip and the other is to integrate both parts with bump bonding or wire bonding after manufacturing both parts separately. The latter method has an advantage of the high yield because the optimized and specialized fabrication process can be chosen in designing and manufacturing each part. In this paper, LACIS chip, that is optimized design for the latter method of fabrication, is presented. The LACIS chip consists of a 3-TR pixel photodiode array, row driver (or called as a gate driver) circuit, and bonding pads to the external readout ICs. Among 4 types of the photodiode structure available in a standard CMOS process, $N_{photo}/P_{epi}$ type photodiode showed the highest quantum efficiency in the simulation study, though it requires one additional mask to control the doping concentration of $N_{photo}$ layer. The optimized channel widths and lengths of 3 pixel transistors are also determined by simulation. The select transistor is not significantly affected by channel length and width. But source follower transistor is strongly influenced by length and width. In row driver, to reduce signal time delay by high capacitance at output node, three stage inverter drivers are used. And channel width of the inverter driver increases gradually in each step. The sensor has very long metal wire that is about 170 mm. The repeater consisted of inverters is applied proper amount of pixel rows. It can help to reduce the long metal-line delay.

Improved breakdown characteristics of Ga2O3 Schottky barrier diode using floating metal guard ring structure (플로팅 금속 가드링 구조를 이용한 Ga2O3 쇼트키 장벽 다이오드의 항복 특성 개선 연구)

  • Choi, June-Heang;Cha, Ho-Young
    • Journal of IKEEE
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    • v.23 no.1
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    • pp.193-199
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    • 2019
  • In this study, we have proposed a floating metal guard ring structure based on TCAD simulation in order to enhance the breakdown voltage characteristics of gallium oxide ($Ga_2O_3$) vertical high voltage switching Schottky barrier diode. Unlike conventional guard ring structures, the floating metal guard rings do not require an ion implantation process. The locally enhanced high electric field at the anode corner was successfully suppressed by the metal guard rings, resulting in breakdown voltage enhancement. The number of guard rings and their width and spacing were varied for structural optimization during which the current-voltage characteristics and internal electric field and potential distributions were carefully investigated. For an n-type drift layer with a doping concentration of $5{\times}10^{16}cm^{-3}$ and a thickness of $5{\mu}m$, the optimum guard ring structure had 5 guard rings with an individual ring width of $1.5{\mu}m$ and a spacing of $0.2{\mu}m$ between rings. The breakdown voltage was increased from 940 V to 2000 V without degradation of on-resistance by employing the optimum guard ring structure. The proposed floating metal guard ring structure can improve the device performance without requiring an additional fabrication step.

Electrochemical properties of $Gd_{0.8}Ca_{0.2}Co_{1-x}Fe_xO_3$ cathodes for medium-temperature SOFC (중간온도형 고체산화물 연료전지의 양극재료로서 $Gd_{0.8}Ca_{0.2}Co_{1-x}Fe_xO_3$의 전기화학특성)

  • Ryu Ji-H.;Jang Jong-H.;Lee Hee-Y.;Oh Seung-M.
    • Journal of the Korean Electrochemical Society
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    • v.1 no.1
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    • pp.1-7
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    • 1998
  • For the purpose of finding new cathode materials for medium-temperature $(700\~800^{\circ}C)$ solid oxide fuel cells, $Gd_{0.8}Ca_{0.2}Co_{1-x}Fe_xO_3,\;(x=0.0\~0.5)$ are prepared, and their thermal stability and conductivity characteristics are investigated. Also, the cathodic activities are measured after the cathode layer being attached on CGO (cerium-gadolinium oxide) electrolyte disk. The X-ray analyses indicate that the materials prepared by calcining the citrate-gels at $800^{\circ}C$ have the orthorhombic perovskite structure without discernible impurities. The thermal stability of the undoped Co perovskite is so poor that it is decomposed to the individual binary oxide even at $1300^{\circ}C$. But the partially Fe-doped cobaltates exhibit a better thermal stability to retain their structural integrity up to $1400^{\circ}C$. The observation whereby both the undoped and Fe-doped cobaltates melt at ca. $1300^{\circ}C$ leads us to perform the electrode adhesion at <$1300^{\circ}C$. The cathodic activity of $Gd_{0.8}Ca_{0.2}Co_{1-x}Fe_xO_3,\;(x=0.0\~0.5)$, electrodes is superior to $La_{0.9}Sr_{0.1}MnO_3$, among the samples of $x=0.0\~0.5$, the x=0.2 cathode shows the best activity for the oxygen reduction reaction. It is likely that the Fe-doping provides a better thermal stability to the materials but in turn imparts an inferior cathodic activity, such that the optimum trade-off is made at x=0.2 between the two factors. The total electrical conductivity and ion conductivity of $Gd_{0.8}Ca_{0.2}Co_{1-x}Fe_xO_3$, are measured to be 51 S/cm and $6.0\times10^{-4}S/cm\;at\;800^{\circ}C$, respectively. The conductivity values illustrate that the materials are a mixed conductor and the reaction sites can be expanded to the overall electrode surface, thereby providing a better cathodic activity than $La_{0.9}Sr_{0.1}MnO_3$.