• 제목/요약/키워드: lateral double-diffused MOSFET (LDMOSFET)

검색결과 3건 처리시간 0.029초

CMOS 공정으로 구현한 고전압 LDMOSFET의 전기적 특성 (Electrical Characteristics of High-Voltage LDMOSFET Fabricated by CMOS Technology)

  • 박훈수;이영기;권영규
    • 한국전기전자재료학회:학술대회논문집
    • /
    • 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
    • /
    • pp.201-202
    • /
    • 2005
  • The electrical characteristics of high-voltage LDMOSFET (Lateral Double-diffused MOSFET) fabricated by a CMOS technology were investigated depending on the process and design parameters. The off-state breakdown voltages of n-channel LDMOSFETs were linearly increased with increasing to the drift region length. For the case of decreasing n-well ion implant doses from $1.0\times10^{13}/cm^2$ to $1.0\times10^{12}/cm^2$, the off-state breakdown voltage was increased approximately two times, however, the on-resistance was also increased about 76%. Moreover, the on- and off-state breakdown voltages were also linearly increased with increasing the channel to n-tub spacing due to the reduction of impact ionization at the drift region.

  • PDF

RESURF type의 SOI n-LDMOSFET 소자 설계 및 제작 (The Design and Fabrication of RESURF type SOI n-LDMOSFET)

  • 김재석;김범주;구진근;구용서;안철
    • 대한전자공학회:학술대회논문집
    • /
    • 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
    • /
    • pp.355-358
    • /
    • 2004
  • In this work, N-LDMOSFET(Lateral Double diffused MOSFET) was designed and fabricated on SOI(Silicon-On-Insulator) substrate, for such applications as motor controllers and high voltage switches, fuel injection controller systems in automobile and SSR(Solid State Rexay)etc. The LDMOSFET was designed to overcome the floating body effects that appear in the conventional thick SOI MOS structure by adding p+ region in source region. Also, RESURF(Reduced SURface Field) structure was proposed in this work in order to reduce a large on-resistance of LDMOSFET when operated keeping high break down voltage. Breakdown voltage was 268v in off-state ($V_{GS}$=OV) at room temperature in $22{\mu}m$ drift length LDMOSFET. When 5V of $V_{GS}$ and 30V of $V_{DS}$ applied, the on resistance(Ron), the transcon ductance($G_m$) and the threshold voltage($V_T$) was 1.76k$\Omega$, 79.7uA/V and 1.85V respectively.

  • PDF

A New SOI LDMOSFET Structure with a Trench in the Drift Region for a PDP Scan Driver IC

  • Son, Won-So;Kim, Sang-Gi;Sohn, Young-Ho;Choi, Sie-Young
    • ETRI Journal
    • /
    • 제26권1호
    • /
    • pp.7-13
    • /
    • 2004
  • To improve the characteristics of breakdown voltage and specific on-resistance, we propose a new structure for a LDMOSFET for a PDP scan driver IC based on silicon-on-insulator with a trench under the gate in the drift region. The trench reduces the electric field at the silicon surface under the gate edge in the drift region when the concentration of the drift region is high, and thereby increases the breakdown voltage and reduces the specific on-resistance. The breakdown voltage and the specific on-resistance of the fabricated device is 352 V and $18.8 m{\Omega}{\cdot}cm^2$ with a threshold voltage of 1.0 V. The breakdown voltage of the device in the on-state is over 200 V and the saturation current at $V_{gs}=5V$ and $V_{ds}$=20V is 16 mA with a gate width of $150{\mu}m$.

  • PDF