• 한국전기전자재료학회논문지
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• 제18권5호
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• pp.401-406
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• 2005

Two dimensional MEDICI simulator is used to study the electrical characteristics of Dual Gate Emitter Switched Thyristor. The simulation is done in terms of the current-voltage characteristics with the variations of p-base impurity concentrations and current flow. Compared with the other power devices such as MOS Controlled Cascade Thyristor(MCCT), Conventional Emitter Switched Thyristor(C-EST) and Dual Channel Emitter Switched Thyristor(DC-EST), Dual Gate Emitter Switched Thyristor(DG-EST) shows to have tile better electrical characteristics, which is the high latch-up current density and low forward voltage-drop. The proposed DG-EST which has a non-planer u-base structure under the floating N+ emitter indicates to have the better characteristics of latch-up current and breakover voltage in spite of the same turn-off characteristics.

• Transactions on Electrical and Electronic Materials
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• 제2권4호
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• pp.15-18
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• 2001

A new small scaling Lateral Trench Insulated Gate Bipolar Transistor (SSLTIGBT) was proposed to improve the characteristics of the device. The entire electrode of the LTIGBT was replaced with a trench-type electrode. The LTIGBT was designed so that the width of device was no more than 10 ${\mu}{\textrm}{m}$. The latch-up current densities were improved by 4.5 and 7.6 times, respectively, compared to those of the same sized conventional LTIGBT arid the conventional LTIGBT which has the width of 17 ${\mu}{\textrm}{m}$. The enhanced latch-up capability of the SSLTIGBT was obtained due to the fact that the hole current in the device reaches the cathode via the p+ cathode layer underneath the n+ cathode layer, directly. The forward blocking voltage of the SSLTIGBT was 125 V. At the same size, those of the conventional LTIGBT and the conventional LTIGBT with the width of 17 ${\mu}{\textrm}{m}$ were 65 V and 105 V, respectively. Because the proposed device was constructed of trench-type electrodes, the electric field In the device were crowded to trench oxide. Thus, the punch through breakdown of LTEIGBT occurred late.

• 대한기계학회논문집A
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• 제38권11호
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• pp.1215-1220
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• 2014

회로차단기에서 가장 중요한 성능은 전기시스템의 이상전류를 신속하게 차단하는 것이다. 이러한 차단시간은 조작기구의 동적 특성에 의한 영향을 받는다. 따라서 회로차단기의 차단시간 단축을 위해서는 조작기구의 최적화가 이루어져야 한다. 본 논문의 가스회로차단기의 조작기는 스프링으로 구동되며 여러 개의 Latch 로 구성되어있다. Latch 들의 상대적 위치와 길이로 정의된 각 설계변수의 차단시간에 대한 영향을 분석하고 이 결과를 통해 설계변수를 선정하여 ADAMS 와 VisualDOC 의 연동을 통해 최적화를 수행하였다. Latch 들의 최적화를 통해 약 22.5% 개극시간을 향상을 확인하였다.

• 전기전자학회논문지
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• 제2권1호
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• pp.101-107
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• 1998

인(Phosphorus)을 1MeV로 이온 주입한 후 RTA를 실시하여 미세결함의 특성을 조사하고, 면저항, SRP, SIMS, XTEM 분석과 CMOS 구조에서 래치업 특성을 모의 실험하였다. 도즈량이 증가할수록 면저항은 낮아지고, Rp값은 도즈량이 $1{\times}10^{13}/cm^2,\;5{\times}10^{13}/cm^2,\;1{\times}10^{14}/cm^2$일때 각각 $1.15{\mu}m,\;1.15{\mu},\;1.10{\mu}m$로 나타났다. SIMS 측정결과는 열처리 시간이 길수록 농도의 최대치가 표면으로부터 깊어지고, 농도 또한 낮아짐을 확인하였다. XTEM 분석 결과는 열처리 전에는 결함측정이 불가능했으나, 측정되지 많은 미세결함이 열처리 후 이차결함으로 성장한 것으로 조사되었다. 모의 실험은 buried layer와 connecting layer 구조를 사용하였으며, buried layer보다 connecting layer가 래치업 특성이 우수함을 확인하였다. Connecting layer의 도즈량이 $1{\times}10^{14}/cm^2$이고 이온주입 에너지가 500KeV일 때 trigger current는 $0.6mA/{\mu}m$이상이었고, trigger voltage는 약 6V로 나타났다. Connecting layer의 이온주입 에너지가 낮을수록 래치업 저감효과가 더욱 우수함을 알 수 있었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.1315-1316
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• 2007

This is paper, a new structure to effectively improve the Vce(sat) voltage and latch-up current in NPT type IGBTs with hole barrier layer and diverter. The hole barrier layer acts as a barrier to prevent the holes from flowing into the p-layer and stores them in the n-layer. And the diverter significantly reduce hole current from flowing into the p-layer and improve latch up current. Analysis on the Breakdown voltage shows identical values compared to existing Conventional IGBT structures. This shows an improvement on Vce(sat) and Latct-up current without lowering other characteristics of the device. The electrical characteristics were studied by MEDICI simulation results.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2018년도 전력전자학술대회
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• pp.539-548
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• 2018

• 조명전기설비학회논문지
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• 제27권10호
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• pp.75-79
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• 2013

The automatic quiescent power cut-off receptacles(QPCR from now on) have achieved a noticeable energy saving so far. The government is preparing a new code for wider promotion of the QPCRs. This paper presents a new QPCR that adopts the latch relay instead of the conventional coil-operated relay. Measurement results of the prototype have shown up to 0.22W improvement of quiescent power compared with existing products.

• 대한전자공학회논문지
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• 제21권5호
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• pp.46-54
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• 1984

3μm 게이트 길이를 가지는 n-well CMOS 공정이 개발되었고 이의 응용 가능성을 검토하였다. Thres-hold 전압은 이온주입으로 쉽게 조절할 수 있으며, 3μm 채널 길이에서 short 채널 효과는 무시할 수 있다. Contact 저항에 있어서 Al-n+ 저항값이 커서 VLSI 소자의 제작에 장애 요인이 될 것으로 보인다. CMOS inverter의 transfer 특성은 양호하며, (W/L) /(W/L) =(10/5)/(5/5)인 89단의 ring oscillator로부터 구한 게이트당 전달 지연 시간은 3.4nsec 정도이다. 본 공정의 설계 규칙에서 n-well과 p-substrate에 수 mA의 전류가 흐를 때 latch-up이 일어나며, well 농도와 n+소오스-well간의 간격에 크게 영향을 받는다. 따라서 공정과 설계 규칙의 변화에 따른 latch-up 특성에 집중적인 연구가 필요할 것으로 사료된다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.805-808
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• 2005

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD(Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low power consumption at same time. maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps, Also, the LIGCSCR(Latch-up Immune Gate Coupled SCR)was designed. It consists of PLVTSCR (P-type Low Voltage Trigger SCR), control NMOS and RC network. The triggering voltage was simulated to 3.6V. And the latch-up characteristics were improved. Finally, we performed the layout high speed I/O interlace circuit with the low triggered ESD protection device in one-chip.

• Transactions on Electrical and Electronic Materials
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• 제5권4호
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• pp.129-132
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• 2004

The electrothermal characteristics of a high voltage LIGBT(Lateral Insulated Gate Bipolar Transistor) using thin silicon on insulator (SOI) and silicon on sapphire (SOS) such as thermal conductivity and sink is analyzed by MEDICI. The device simulations demonstrate that the thermal conductivity of the buried oxide is an important parameter for modeling of the thermal behavior of SOI devices. In this paper we simulated the thermal conductivity and temperature distribution of a SOI LIGBT with an insulator layer of SiO$_2$ and $Al_2$O$_3$ at before and after latch-up and verified that the SOI LIGBT with the $Al_2$O$_3$ insulator had good thermal conductivity and reliability.