• 한국전기전자재료학회논문지
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• 제16권7호
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• pp.584-592
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• 2003

6H-SiC MOSFETs and digital ICs have been fabricated and characterized. PMOS devices are fabricated on an n-type epilayer while the NMOS devices are fabricated on implanted p-wells. NMOS and PMOS devices use a thermally grown gate oxide. SiC MOSFETs are fabricated using different impurity activation methods such as high temperature and newly proposed laser annealing methods. Several digital circuits, such as resistive road NMOS inverters, CMOS inverters, resistive road NMOS NANDs and NORs are fabricated and characterized.

• 한국전기전자재료학회논문지
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• 제22권6호
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• pp.462-465
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• 2009

Schottky barrier thin film transistors (SB-TFT) on polycrystalline silicon(poly-Si) are fabricated by platinum silicided source/drain for p-type SB-TFT. High quality poly-Si film were obtained by crystallizing the amorphous Si film with excimer laser annealing (ELA) or solid phase crystallization (SPC) method, The fabricated poly-Si SB-TFTs showed low leakage current level and a large on/off current ratio larger than 10), Significant improvement of electrical characteristics were obtained by the additional forming gas annealing in 2% $H_2/N_2$ ambient, which is attributed to the termination of dangling bond at the poly-Si grain boundaries as well as the reduction of interface trap states at gate oxide/poly-Si channel.

• 대한기계학회논문집A
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• 제20권6호
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• pp.1827-1835
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• 1996

This paper addresses the problem of a torch path generation for the 2D laser cutting of a stock plate nested with resular or irregular parts. Under the constaint of the relative positions of parts enforced by nesting, the developed torch path algorithm generate feasible cutting path. In this paper, the basic object is a polygon( a many-slide figure) with holes. A part may be represented as a number of line segments connected end-to-end in counterclockwise order, and formed a closed contour as requied for cutting paths. The objective is to tranverse this cutting contours with a minimum path length. This paper proposes a simulated annealing based dtorch path algorithm, that is an improved version of previously suggested TSP models. Since everypiercing point of parts is not fixed in advance, the algorithm solves as relazed optimization problem for the constraint, thich is one of the main features of the proposed algorithm. For aolving the torch path optimization problem, an efficient generation mechanism of neighborhood structure and as annealing shedule were introduced. In this way, a global solution can be obtained in a reasonable time. Seveeral examples are represented to ilustrate the method.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제49권1호
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• pp.24-29
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• 2000

We propose a simple method to control the crystallization depth of amorphous silicon (a-Si) deposited by PECVD or LPCVD during the excimer laser annealing (ELA). Employing the new method, we have formed poly-Si/a-Si double film and fabricated a new poly-Si TFT with vertical a-Si offsets between the poly-Si channel and the source/drain of TFT without any additional photo-lithography process. The maximum leakage current of the new poly-Si TFT decreased about 80% due to the highly resistive vertical a-Si offsets which reduce the peak electric field in drain depletion region and suppress electron-hole pair generation. In ON state, current flows spreading down through broad a-Si cross-section in the vertical a-Si offsets and the current density in the drain depletion region where large electric field is applied is reduced. The stability of poly-Si TFT has been improved noticeably by suppressing trap state generation in drain region which is caused by high current density and large electric field. For example, ON current of the new TFT decreased only 7% at a stress condition where ON current of conventional TFT decreased 89%.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 Techno-Fair 및 추계학술대회 논문집 전기물성,응용부문
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• pp.88-89
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• 2007

ZnO thin films were deposited on $Al_2O_3$ (alumina) substrates by pulsed laser deposition (PLD) using Nd:YAG laser with a wavelength of 355nm, at room temperature and oxygen partial pressure of 1, 10, 30, 50, 100, and 200m Torr. Furthermore, deposited ZnO thin films were post-annealed at 400, 550, $600^{\circ}C$. The effects of oxygen partial pressure and post-annealing temperature on structural properties of the deposited films have been investigated by means of X-ray diffraction (XRD), and atomic force microscope (AFM), respectively. It has been found that ZnO thin films exhibit c-axis orientation, exhibiting an increased foil width at half maximum (FWHM) value of (002) diffraction peak at 30m Torr oxygen partial pressure and higher post-annealing temperature ($700^{\circ}C$).

• 한국통신학회논문지
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• 제18권3호
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• pp.449-455
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• 1993

단거리 통신 시스팀의 광원으로 유용한 단파장 AlGaAs/GaAs레이저 다이오우드의 열악한 특성을 개선하기 위하여 MBE에 의해 낮은 온도에서 성장한 AlGaAs/GaAs GRINSCH-QW 레이저 다이오우드를 RTA온도의 변화에 좌우되는 포토루미네센스에 의하여 연구하였다. $950^{\circ}C$에서 10초동안 RTA처리를 한후 양자우물 포토루미네센스의 세기는 대체로 10배정도 증가하는것을 보여주었다. 이것은 양자우물 영역에서 발광되지 않는 재결합이 감소된것과 관련된다. 열처리된 레이저 다이오우드의 임계전류는 4배로 감소되었으며 RTA에 의하여 레이저 다이오우드의 질이 개선되었음이 확인되었다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제48권9호
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• pp.623-627
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• 1999

We report a new in-situ fluorine passivation method without in implantation by employing excimer laser annealing of $SiO_{x}F_{y}$/a-Si structure and its effects on p-channel poly-Si TFTs. The proposed method doesn't require any additional annealing step and is a low temperature process because fluorine passivation is simultaneous with excimer-laser-induced crystallization. A in-situ fluorine passivation by the proposed method was verified form XPS analysis and conductivity measurement. From experimental results, it has been shown that the proposed method is effective to improve the electrical characteristics, specially field-effect mobility, and the electrical stability of p-channel poly-Si TFTs. The improvement id due to fluorine passivation, which reduces the trap state density and forms the strong Si-F bonds in poly-Si channel and $SiO_2/poly-Si$ interface. From these results, the high performance poly-Si TFTs canbe obtained by employing the excimer-laser-induced fluorine passivation method.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2016년도 추계학술대회 논문집
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• pp.134-134
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• 2016

The effect of different thermal treatments on the sub-50 nm copper nanoparticles is examined in the aspects of chemical, electrical and surface morphology. The copper nanoparticles are chemically synthesized and fabricated for paste-type solution. Simple bar coating method is practiced as a deposition process to form copper thin film on a typical slide glass. Deposited copper thin films are annealed by two different routes: general tube furnace with 99.99 % Ar atmosphere and selective laser sintering process. The thermal behavior of the different thermal-treated copper thin films is compared by SEM, XRD, FT-IR and XPS analysis. In this study, the laser sintering process ensures low annealing temperature, fast working speed and ambient-accessible route. Moreover, the laser-sintered copper thin film shows good electrical property and enhanced chemical stability than conventional thermal annealing process. Consequently, the proposed laser sintering process can be compatible with plastic substrate for flexible applications.

• Journal of the Optical Society of Korea
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• 제20권5호
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• pp.575-578
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• 2016

The thermal endurance of fiber Bragg gratings (FBGs), written with the aid of 193-nm ArF excimer laser irradiation on H₂-loaded Ge/B codoped silica fiber, and pretreated with a CO₂ laser and a subsequent slow cooling process, is investigated. These treated gratings show relatively less degradation of grating strength during the thermal annealing procedure. The thermal decay characteristics of treated and untreated fiber, recorded over a time period of 9 hours, have been compared. The effect on the Bragg transmission depth (BTD) and the center-wavelength shift, as well as the growth of refractive-index change during the grating inscription process for both treated and untreated fiber, are analyzed.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.562-565
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• 2001

In this paper, novel device structures in order to realize ultra fast and ultra small silicon devices are investigated using ultra-high vacuum chemical vapor deposition(UHVCVD) and Excimer Laser Annealing (ELA). Based on these fundamental technologies for the deep sub-micron device, high speed and low power devices can be fabricated. These junction formation technologies based on damage-free process for replacing of low energy ion implantation involve solid phase diffusion and vapor phase diffusion. As a result, ultra shallow junction depths by ELA are analyzed to 10~20nm for arsenic dosage(2${\times}$10$\_$14//$\textrm{cm}^2$), exciter laser source(λ=248nm) is KrF, and sheet resistances are measured to 1k$\Omega$/$\square$ at junction depth of 15nm and realized sub-50nm n-MOSFET.