• 에너지공학
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• 제8권4호
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• pp.592-604
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• 1999

대면적 용융탄산염 연료전지 운전 시 스택에서 발생하는 스택내 온도차와 극간 차압의 문제점을 해결하기 위하여 정상상태특성 및 동특성을 분석하였다. 두가지 용융탄산염연료전지 스택(5 kW(3,000$\textrm{cm}^2$, 20장), 3kW(6,000$\textrm{cm}^2$, 5장) 의 운전결과를 통하여 스택성능에 중요한 영향을 미치는 조작변수(전류밀도 , 연료 이용률, 공기 이용률)와 조절변수(스택 온도차, 연료극 차압, 공기극 차압)를 결정하였다. 조작변수들에 대한 조절변수들의 변화량인 스택의 정상상태 이득률을 구하여 시스템의 안정성을 분석하고 동특성을 나타내는 전달함수를 구하였따. 전달함수는 3$\times$3 행렬로 시간 지연항이 없는 전형적인 1차 시스템으로 표현되었다 동특성 분석에 의해 대면적 용융탄산염 연료전지 시스템의 최적 운전 조건을 설정할 수 있었다. 5 kW 스택의 경우 전류밀도가 150mA/$\textrm{cm}^2$ 일 때 스택 출구 온도를 68$0^{\circ}C$ 이하로 유지하기 위해서는 공기극 가스 recycle 에 의한 가압 운전이 필요하였으며, 효과적으로 용융탄산염 연료전지 시스템을 제어하기위해서는 조작변수의 조절변수상호간의 연계성을 제거하기위한 다중 입.출력 제어 및 연계 제거기가 필요함을 확인하였다. 이 결과는 향후 대면적 용융탄산염을 연료전지 시스템의 제어구조 설계와 운전모드설정에 중요한 자료로 사용될 것이다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 하계학술대회 논문집 C
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• pp.1308-1310
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• 1997

Several methods for electrode fabrication of phosphoric acid fuel cell(PAFC) have been studied. The conventional methods that include a coating method and a rolling method, have disadvantages of a very complicated drying process and a hot pressing process for making a large electrode. In this study, to solve these problems, the mixing method of coating and rolling processes has been developed. In the mixing method, the electrode was coated on the electrode support and, after drying the coated layer, was rolled at room temperature and then sintered at $350^{\circ}C$. The single cell performances of the electrodes fabricated by several methods were examined and the mixing method appeared a good cell performance of 0.65 V, $260\;mA/cm^2$. Also the single cell with an area of $2000\;cm^2$ was manufactured and its performance attained 0.593 V, 300 A.

• 한국컴퓨터산업학회논문지
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• 제6권5호
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• pp.757-766
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• 2005

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6T Full CMOS SRAM had been continued as the technology advances, However, conventional 6T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6T Full CMOS SRAM is $70{\sim}90F^{2}$, which is too large compared to $8{\sim}9F^{2}$ of DRAM cell. With 80nm design rule using 193nm ArF lithography, the maximum density is 72M bits at the most. Therefore, pseudo SRAM or 1T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed $S^{3}$ cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^{3}$ SRAM cell technology with 100nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• 한국전기전자재료학회논문지
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• 제19권4호
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• pp.314-321
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• 2006

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6 T Full CMOS SRAM had been continued as the technology advances. However, conventional 6 T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6 T Full CMOS SRAM is $70{\sim}90\;F^2$, which is too large compared to $8{\sim}9\;F^2$ of DRAM cell. With 80 nm design rule using 193 nm ArF lithography, the maximum density is 72 Mbits at the most. Therefore, pseudo SRAM or 1 T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64 M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6 T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed S3 cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^3$ SRAM cell technology with 100 nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제10권8호
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• pp.3529-3550
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• 2016

In heterogeneous networks (HetNets), energy saving is vital for a sustainable network development. Many techniques, such as spectrum allocation, network planning, etc., are used to improve the network energy efficiency (EE). In this paper, micro BSs utilizing cell range expansion (CRE) and spectrum allocation are considered in multi-channel heterogeneous networks to improve EE. Hotspot region is assumed to be covered by micro BSs which can ensure that the hotspot capacity is greater than the average demand of hotspot users. The expressions of network energy efficiency are derived under shared, orthogonal and hybrid subchannel allocation schemes, respectively. Particle swarm optimization (PSO) algorithm is used to solve the optimal ratio of subchannel allocation in orthogonal and hybrid schemes. Based on the results of the optimal analysis, we propose three service control strategies on the basis of large-scale user behaviors, i.e., adjust micro cell rang expansion (AmCRE), adjust micro BSs density (AmBD) and adjust micro BSs transmit power (AmBTP). Both theoretical and simulation results show that using shared subchannel allocation scheme in AmBD strategies can obtain maximal EE with a very small area ratio. Using orthogonal subchannel allocation scheme in AmCRE strategies can obtain maximal EE when area ratio is larger. Using hybrid subchannel allocation scheme in AmCRE strategies can obtain maximal EE when area ratio is large enough. No matter which service control strategy is used, orthogonal spectrum scheme can obtain the maximal hotspot user rates.

• Transactions on Electrical and Electronic Materials
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• 제5권1호
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• pp.1-6
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• 2004

Zinc sulfide is a semiconductor with wide band gap and high refractive index and hence promising material to be used as ARC on commercial silicon solar cells. Uniform deposition of zinc sulfide (ZnS) by using chemical bath deposition (CBD) method over a large area of silicon surface is an emerging field of research because ZnS film can be used as a low cost antireflection coating (ARC). The main problem of the CBD bath process is the huge amount of precipitation that occurs during heterogeneous reaction leading to hamper the rate of deposition as well as uniformity and chemical stoichiometry of deposited film. Molar concentration of thiorea plays an important role in varying the percentage of reflectance and refractive index of as-deposited CBD ZnS film. Desirable rate of film deposition (19.6 ${\AA}$ / min), film uniformity (Std. dev. < 1.8), high value of refractive index (2.35), low reflectance (0.655) have been achieved with proper optimization of ZnS bath. Decrease in refractive index of CBD ZnS film due to high temperature treatment in air ambiance has been pointed out in this paper. Solar cells of conversion efficiency 13.8 ％ have been successfully achieved with a large area (103 mm ${\times}$ 103 mm) mono-crystalline silicon wafers by using CBD ZnS antireflection coating in this modified approach.

• 한국진공학회지
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• 제5권4호
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• pp.341-347
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• 1996

Spray pyrolysis 방법으로 넓은 면적의 $Cu_2S$/CdS 태양전지를 제작하였다. 제작과정에서 전극형성, CdS spray 온도조건, $Cu_2S$층의 접합 조건등 태양전지의 효율에 영향을 주는 요인을 조사하였다. CdS 박막의 조건은 주사 전자현미경, X-선 회절기, 온도변화에 따른 광흡수 및 관전도 특성등을 통해 결정하였다. 1$\textrm{cm}^2$의 면적의 전지에 air mass 2(AM2)인 75mW/$\textrm{cm}^2$로 빛을 조사했을 때 3.15%의 효율을 얻었다.

• Nuclear Engineering and Technology
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• 제49권8호
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• pp.1717-1726
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• 2017

In the nuclear industry, mechanical engineers spend a significant portion of their time designing equipment such as manipulators, bogies, mechanical grippers, and so on. Some customized designs can be considered as standard mechanical equipment in this area, although it is not unusual to find that an existing design cannot simply be copied from one project to another. Varied performance requirements can dictate that redesign, often quite extensive redesign, is required. However, if something similar has been done before, engineers could use that as a starting point for the new project. In this regard, this study presents several guidelines inspired by previous design knowledge for similar development cases. Moreover, this study presents more detailed suggestions such as design guidelines for an argon-based hot cell atmosphere and design experience for a large-scale practical hot cell facility. Design considerations and case studies dealt with in this study are dedicated to teleoperation manipulators that are used at a large-scale argon cell facility for pyroprocess integrated inactive demonstration (PRIDE), at the Korea Atomic Energy Research Institute. In particular, for case studies to support the suggested recommendations, a fabricated telemanipulator system for PRIDE is introduced, and several kinds of experimental results associated with it are presented.

• Journal of Electrochemical Science and Technology
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• 제13권1호
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• pp.112-119
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• 2022

Molten carbonate fuel cells (MCFCs) are environmentally friendly, large-capacity power generation devices operated at approximately 650℃. If MCFCs are to be commercialized by improving their competitiveness, their cell life should be increased by operating them at lower temperatures. However, a decrease in the operating temperature causes a reduction in the cell performance because of the reduction in the electrochemical reaction rate. The cell performance can be improved by introducing a coating on the cathode of the cell. A coating with a high surface area expands the triple phase boundaries (TPBs) where the gas and electrolyte meet on the electrode surface. And the expansion of TPBs enhances the oxygen reduction reaction of the cathode. Therefore, the cell performance can be improved by increasing the reaction area, which can be achieved by coating nanosized LiCoO₂ particles on the cathode. However, although a coating improves the cell performance, a thick coating makes gas difficult to diffuse into the pore of the coating and thus reduces the cell performance. In addition, LiCoO₂-coated cathode cell exhibits stable cell performance because the coating layer maintains a uniform thickness under MCFC operating conditions. Therefore, the performance and stability of MCFCs can be improved by applying a LiCoO₂ coating with an appropriate thickness on the cathode.

• Journal of Electrical Engineering and Technology
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• 제3권1호
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• pp.130-134
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• 2008

The increasing size of very large scale integration (VLSI) circuits, high transistor density, and popularity of low-power circuit and system design are making the minimization of power dissipation an important issue in VLSI design. Test Power dissipation is exceedingly high in scan based environments wherein scan chain transitions during the shift of test data further reflect into significant levels of circuit switching unnecessarily. Scan chain or cell modification lead to reduced dissipations of power. The ETC algorithm of previous work has weak points. Taking all of this into account, we therefore propose a new algorithm. Its name is RE_ETC. The proposed modifications in the scan chain consist of Exclusive-OR gate insertion and scan cell reordering, leading to significant power reductions with absolutely no area or performance penalty whatsoever. Experimental results confirm the considerable reductions in scan chain transitions. We show that modified scan cell has the improvement of test efficiency and power dissipations.