• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.765-768
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• 2008

To make 3D camera system, we check the possibility of advanced range camera module based on measuring the time delay of modulated infrared light, using a single detector chip fabricated on standard CMOS process. To depth information, electronic shutter and interlaced scanning method of 2D sensor is needed. Especially, we design "lens system, illumination unit" and review simulation result.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.297-300
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• 1987

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.6
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• pp.175-181
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• 2019

For the purpose of Application to the small radar sensor, the MMIC Chip, which is the core component of the W-band, was designed in Korea according to the characteristics of the transceiver and manufactured by 0.1㎛ GaAs pHEMT process, and compared with the MMIC chip purchased overseas. The noise figure of low noise amplifier, insertion loss of the switch and image rejection performance of the down-converted mixer MMIC chip showed better characteristics than those of commercial chips. The MMIC chip developed in domestic was applied to the transmitter and receiver through W-band waveguide low loss transition structure design and impedance matching to verify the performance after the fabrication is 9.17 dB, which is close to the analysis result. As a result, it is judged that the transceiver can be applied to the small radar sensor better than the MMIC chip purchased overseas.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.669-670
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• 2006

This paper describes the functions and design technology of the T-DMB (Terrestrial Digital Multimedia Broadcasting) receiver. T-DMB is a novel broadcasting media that can provide high-quality video and audio services. In this paper, we will describe the VLSI implementation of RF, Baseband and Multimedia Chip for T-DMB Receiver. The designed DMB SoC has low power consumption and has been implemented using a standard-cell library in 0.18um CMOS technology.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.1663-1667
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• 2003

This thesis is on tile development of LD(Laser Diode) chip tester and the control system based on graphical programming language(LabVIEW) to control the equipment. The LD chip tester is used to test the optic power and the optic spectrum of the LD Chip. The emitter size of LD chip and the diameter of the receiver(optic fiber) are very small. Therefore, in order to test each chip precisely, this tester needs high accuracy. However each motion part of the tester could not accomplish hish accuracy due to the limit of the mechanical performance. Hence. an image processing with machine vision was carried out in order to compensate for the error. and also a load test was carried out so as to reduce tile impact of load on chip while the probing motion device is working. The obtained results were within ${\pm}$5$\mu\textrm{m}$ error.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2003.11a
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• pp.69-72
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• 2003

This paper presents a signal processing IC for digital HDTV, which is designed to operate in bunt-in HDW or in HD-set-top Box. The chip supports de-multiplexing an ISO/IEC 13818-1 MPEG-2 TS stream. It decodes MPEG-2 MP@HL video bitstream, and provides high-quality scaled video for display on HDTV monitor. The chip consists of ARM7TDMI for TS-Demux, PCI interface, Audio interface, MPEG2 MP@HL video decoder Display processor, Graphic processor, Memory controller, Audio int3face, Smart Card interface and UART. It is fabricated using Sam sung's 0.18-um and the package of 492-pin BGA is used.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.9
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• pp.1158-1165
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• 2021

This paper proposes a CNN accelerator which is optimized Pooling layer operation incorporated in Multiplication And Accumulation(MAC) to reduce the memory size. For optimizing memory and data path circuit, the quantized 8bit integer weights are used instead of 32bit floating-point weights for pre-training of MNIST data set. To reduce chip area, the proposed CNN model is reduced by a convolutional layer, a 4*4 Max Pooling, and two fully connected layers. And all the operations use specific MAC with approximation adders and multipliers. 94% of internal memory size reduction is achieved by simultaneously performing the convolution and the pooling operation in the proposed architecture. The proposed accelerator chip is designed by using TSMC65nmGP CMOS process. That has about half size of our previous paper, 0.8*0.9 = 0.72mm². The presented CNN accelerator chip achieves 94% accuracy and 77us inference time per an MNIST image.

• 한국생물공학회:학술대회논문집
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• 2001.11a
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• pp.43-43
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• 2001

• Proceedings of the Korean Society of Potoscience Conference
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• spring
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• pp.16-16
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• 2001

• The Magazine of the IEIE
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• v.29 no.3
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• pp.36-40
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• 2002