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http://dx.doi.org/10.6109/jkiice.2021.25.9.1158

Compact CNN Accelerator Chip Design with Optimized MAC And Pooling Layers  

Son, Hyun-Wook (Mixed Signal Integrated System Lab, ChungBuk National University)
Lee, Dong-Yeong (Mixed Signal Integrated System Lab, ChungBuk National University)
Kim, HyungWon (Mixed Signal Integrated System Lab, ChungBuk National University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.25, no.9, 2021 , pp. 1158-1165 More about this Journal
Abstract
This paper proposes a CNN accelerator which is optimized Pooling layer operation incorporated in Multiplication And Accumulation(MAC) to reduce the memory size. For optimizing memory and data path circuit, the quantized 8bit integer weights are used instead of 32bit floating-point weights for pre-training of MNIST data set. To reduce chip area, the proposed CNN model is reduced by a convolutional layer, a 4*4 Max Pooling, and two fully connected layers. And all the operations use specific MAC with approximation adders and multipliers. 94% of internal memory size reduction is achieved by simultaneously performing the convolution and the pooling operation in the proposed architecture. The proposed accelerator chip is designed by using TSMC65nmGP CMOS process. That has about half size of our previous paper, 0.8*0.9 = 0.72mm2. The presented CNN accelerator chip achieves 94% accuracy and 77us inference time per an MNIST image.
Keywords
CNN; SoC design; MAC; MNIST;
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