• Journal of the KSME
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• v.43 no.2
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• pp.43-47
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• 2003

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.11a
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• pp.3-4
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• 2004

A flexible Packaging scheme, which embedded chip packaging, has been developed using a thinned silicon chip. Mechanical characteristics of thinned silicon chips are examined by bending test and finite element analysis. Thinned silicon chips ($t<50{\mu}m$) are fabricated by chemical etching process to avoid possible surface damages on them. These technologies can be use for a real-time monitoring of blood pressure. Our research targets are implantable blood pressure sensor and its telemetric measurement. By winding round the coronary arteries, we can measure the blood pressure by capacitance variation of blood vessel.

• Korean Journal of Optics and Photonics
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• v.28 no.4
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• pp.135-140
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• 2017

In this paper, we report measured results for an all-fiber $7{\times}1$ pump combiner based on an optical fiber chip for high-power fiber lasers. An optical-fiber chip was fabricated by etching a fiber, having core and cladding diameters of 20 and $400{\mu}m$, in the longitudinal direction. To both ends of the etched chip, we spliced input and output fibers. First, we tied together seven optical fibers, having core and cladding diameters of 105 and $125{\mu}m$ respectively, in a cylindrical bundle and spliced them to the $375-{\mu}m$ end of the optical-fiber chip. Then, we attached an output DCF with core and cladding diameters of 25 and $250{\mu}m$ to the $250-{\mu}m$ end of the optical-fiber chip. Finally, the fabricated $7{\times}1$ pump combiner showed an average optical coupling efficiency of about 90.2% per port. This chip-based pump combiner may replace conventional pump combiners by massive production of fiber chips.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.203-207
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• 1999

In this paper we report new integration technology developed for three-dimensional metallic microstructures in an arbitrary shape. We have developed the two fabrication methods: Multi-Exposure and Single-Development (MESD) and Sacrificial Metallic Mold(SMM) techniques. Three-dimensional photoresist mold can be formed by the MESD method while unlimited number of structural levels can be realized by the SMM technique. Using these two techniques we have fabricated solenoid inductors and levitated spiral inductors for RF applications. We have achieved peak Q- factors over 40 in the 2-10㎓ range, the highest number among the inductors reported to date. Finally, we propose "On-Chip Passives" as a post IC process for monolithic integration of inductors, tunable capacitors, microwave switches, transmission lines, and mixers and filters toward future single-chip transceiver integration.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.238-246
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• 2011

A 3-5 GHz UWB radar chip in 0.13 ${\mu}m$ CMOS process is presented in this paper. The UWB radar transceiver for surveillance and biometric applications adopts the equivalent time sampling architecture and 4-channel time interleaved samplers to relax the impractical sampling frequency and enhance the overall scanning time. The RF front end (RFFE) includes the wideband LNA and 4-way RF power splitter, and the analog signal processing part consists of the high speed track & hold (T&H) / sample & hold (S&H) and integrator. The interleaved timing clocks are generated using a delay locked loop. The UWB transmitter employs the digitally synthesized topology. The measured NF of RFFE is 9.5 dB in 3-5 GHz. And DLL timing resolution is 50 ps. The measured spectrum of UWB transmitter shows the center frequency within 3-5 GHz satisfying the FCC spectrum mask. The power consumption of receiver and transmitter are 106.5 mW and 57 mW at 1.5 V supply, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.542-549
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• 2016

This paper presents a SoC (System-on-a-Chip) dedicated for a single-chip smart capsule which can be used to continuously monitor human alimentary canal pH and temperature values. The SoC is composed of the pH and temperature sensor interface circuit, a wireless transceiver, the power management circuit and the flow control logic. Fabricated in $0.18{\mu}m$ standard CMOS technology, the SoC occupies a die area of ${\sim}9 mm^2$. The SoC consumes 6.15 mW from a 3 V power supply, guaranteeing the smart capsule battery life is no less than 24 hours when using 50 mAh coin batteries. The experimental results show that measurement accuracy of the smart capsule is ${\pm}0.1$ pH and ${\pm}0.2^{\circ}C$ for pH and temperature sensing, respectively, which meets the requirement of in-body pH and temperature monitoring in clinical practice.

• ETRI Journal
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• v.35 no.5
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• pp.767-774
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• 2013

In this paper, a novel parallel Viterbi decoding scheme is proposed to decrease the decoding latency and power consumption for the software-defined radio (SDR) system. It implements a divide-and-conquer approach by first dividing a block into a series of subblocks, then performing independent Viterbi decoding for each subsequence, and finally merging the surviving subpaths into the final path. Moreover, a network-on-chip-based SDR platform is used to evaluate the performance of the proposed parallel Viterbi decoding scheme. The experiment results show that our scheme can speed up the Viterbi decoding process without increasing the BER, and it performs better than the current state-of-the-art methods.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.7 no.4
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• pp.267-273
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• 2007

This paper presents the implementation of an educational kit for intelligent system control education. Neural network control algorithms are presented and control hardware is embedded to control the inverted pendulum system. The RBF network and the MLP network are implemented and embedded on the DSP 2812 chip and other necessary functions are embedded on an FPGA chip. Experimental studies are conducted to compare performances of two neural control methods. The intelligent control educational kit(ICEK) is implemented with the inverted pendulum system whose movements of the cart is limited by space. Experimental results show that the neural controllers can manage to control both the angle and the position of the inverted pendulum systems within a limited distance. Performances of the RCT and the FEL control method are compared as well.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.449-450
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• 2008

In this paper, we present the design of a system on a chip(SoC) based on Powerline Communication for Power-IT. The SoC deals with power information obtained from analog to digital converter and transmits this data via powerline. We integrate main processor, ADC and PLC function into a chip. Also a FPGA-based emulation system is introduced to evaluate a proposed SoC architecture.

• 연구논문집
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• s.33
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• pp.17-25
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• 2003

In this work, thermal design of a PCR chip for LOC is systematically conducted. From the numerical simulation of a PCR chip based on the finite volume method, how to control the average temperature of a PCR chip and the temperature difference between the denaturation zone and the annealing zone is presented. The average temperature is shown to be controlled by adjusting heat input and a cooler as well as a heater is shown to be necessary to obtain three individual temperature zones for polymerase chain reaction. To reduce the time required, a heat sink for the cooler is not included in the calculation domain for the PCR chip and heat sink design is conducted separately by using a compact modeling method, the porous medium approach.