• Title/Summary/Keyword: k-코어

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Multi-core Scalable Fair I/O Scheduling for Multi-queue SSDs (멀티큐 SSD를 위해 멀티코어 확장성을 제공하는 공정한 입출력 스케줄링)

  • Cho, Minjung;Kang, Hyeongseok;Kim, Kanghee
    • Journal of KIISE
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    • v.44 no.5
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    • pp.469-475
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    • 2017
  • The emerging NVMe-based multi-queue SSDs provides a high bandwidth by parallel I/O, i.e., each core performs I/O through its dedicated queue in parallel with other cores. To provide a bandwidth share for each application with I/O, a fair-share scheduler that provides a bandwidth share to each core is required. In this study, we proposed a multi-core scalable fair-queuing algorithm for multi-queue SSDs. The algorithm adopts randomization to minimize the inter-core synchronization overheads and provides a weight-proportional bandwidth share to each core. The results of our experiments indicated that the proposed algorithm gives accurate bandwidth partitioning and outperforms the existing FlashFQ scheduler, regardless of the number of cores for a Linux kernel with block-mq.

Sojourn Time Analysis Using SRPT Scheduling for Heterogeneous Multi-core Systems (Heterogeneous 멀티코어 시스템에서 SRPT 스케줄링을 사용한 체류 시간 분석)

  • Yang, Bomi;Park, Hyunjae;Choi, Young-June
    • Journal of KIISE
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    • v.44 no.3
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    • pp.223-231
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    • 2017
  • In this paper, we study the performance of recently popular multi-core systems in mobiles. Previous research on the multi-core performance usually focused on the desktop PC. However, there is enough scope to further analyze heterogeneous multi-core systems. Therefore, by extending homogeneous multi-core systems, we analyze the heterogeneous multi-core systems using Size Interval Task Allocation (SITA) for job allocation, and Shortest Remaining Processing Time (SRPT) scheduling, for each individual core. We propose a new computational method regarding the cutoff point, which is crucial in analyzing SITA, by calculating the sojourn time. This facilitate easy and accurate calculation of the sojourn time. We further confirm our analysis through the ESESC simulator that provides actual measurements.

Probabilistic Power-saving Scheduling of a Real-time Parallel Task on Discrete DVFS-enabled Multi-core Processors (이산적 DVFS 멀티코어 프로세서 상에서 실시간 병렬 작업을 위한 확률적 저전력 스케쥴링)

  • Lee, Wan Yeon
    • Journal of the Korea Society of Computer and Information
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    • v.18 no.2
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    • pp.31-39
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    • 2013
  • In this paper, we propose a power-efficient scheduling scheme that stochastically minimizes the power consumption of a real-time parallel task while meeting the deadline on multicore processors. The proposed scheme applies the parallel processing that executes a task on multiple cores concurrently, and activates a part of all available cores with unused cores powered off, in order to save power consumption. It is proved that the proposed scheme minimizes the mean power consumption of a real-time parallel task with probabilistic computation amount on DVFS-enabled multicore processors with a finite set of discrete clock frequencies. Evaluation shows that the proposed scheme saves up to 81% power consumption of the previous method.

Trends in Lightweight Kernel for Manycore Based High-Performance Computing (매니코어 기반 고성능 컴퓨팅을 지원하는 경량커널 동향)

  • Kim, J.M.;Cha, S.J.;Jeon, S.H.;Koh, K.W.;Jeong, Y.J.;Kim, K.H.;Jung, S.I.
    • Electronics and Telecommunications Trends
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    • v.32 no.4
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    • pp.48-56
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    • 2017
  • 대규모 고성능 컴퓨팅 시스템에서 경량커널은 전통적으로 계산 노드에 탑재되어 특정 연산만을 수행한다. 특히 경량커널은 병렬 프로그램을 실행함에 있어 성능을 최대한 끌어올리기 위하여 자원 간의 간섭을 최소화할 수 있도록 개발되어 사용되고 있다. 최근에는 수천 개의 코어가 장착된 고성능 컴퓨팅 환경은 병렬프로그램뿐만 아니라 일반 응용 및 대규모 분산 응용에서도 필요하다. 고성능 컴퓨팅 환경에서는 매니코어와 메모리 자원이 늘어남에 따라 성능 확장성을 요구하는 현실적인 운영체제의 구조로서 경량커널과 리눅스를 같이 실행하는 멀티커널 구조를 선호하고 있다. 본고에서는 이러한 선행연구를 소개하고 매니코어 시스템에서 활용되는 최근 경량커널의 동향에 대해 살펴본다.

Parallel Programming Model for Manycore (매니코어 병렬프로그래밍 모델)

  • Kim, J.M.;Byun, S.W.;Kim, K.H.;Koh, K.W.;Cha, S.J.;Jeong, Y.J.;Jung, S.I.
    • Electronics and Telecommunications Trends
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    • v.30 no.4
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    • pp.36-45
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    • 2015
  • 매니코어는 단순한 기능을 가진 수백~수천 개 코어를 하나의 CPU에 집적하여 성능을 구현하는 것으로 근본적으로 이를 활용할 병렬프로그래밍이 필요하다. 단순히 속도를 높이는 방향으로 발전하던 하드웨어는 병렬성을 증대하는 방향으로 발전하고 있고 이에 따라 프로그래밍 패러다임 역시 변하고 있다. 병렬화를 위한 여러 기술이 하드웨어에 구현되고 프로그래머가 이를 보다 적극적으로 활용할 수 있게 하는 유용한 병렬프로그래밍 모델이 필요하다. 또한, 컴퓨팅 환경은 자원의 활용도를 중시하는 시스템 중심에서 응용 및 서비스 중심으로 변화하고 있으므로, 그 도메인에 적합하게 프로그래밍할 수 있는 환경이 요구된다. 매니코어에서 병렬시스템 구조를 활용하는 방법을 결정하는 병렬프로그래밍 모델은 그 목적에 유연하게 제공되고 또한 컴퓨팅 환경 변화에 따라 새로운 개념의 모델을 정립하는 데 있어 유용해야 한다.

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Parallel Implementation and Performance Evaluation of the SIFT Algorithm Using a Many-Core Processor (매니코어 프로세서를 이용한 SIFT 알고리즘 병렬구현 및 성능분석)

  • Kim, Jae-Young;Son, Dong-Koo;Kim, Jong-Myon;Jun, Heesung
    • Journal of the Korea Society of Computer and Information
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    • v.18 no.9
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    • pp.1-10
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    • 2013
  • In this paper, we implement the SIFT(Scale-Invariant Feature Transform) algorithm for feature point extraction using a many-core processor, and analyze the performance, area efficiency, and system area efficiency of the many-core processor. In addition, we demonstrate the potential of the proposed many-core processor by comparing the performance of the many-core processor with that of high-performance CPU and GPU(Graphics Processing Unit). Experimental results indicate that the accuracy result of the SIFT algorithm using the many-core processor was same as that of OpenCV. In addition, the many-core processor outperforms CPU and GPU in terms of execution time. Moreover, this paper proposed an optimal model of the SIFT algorithm on the many-core processor by analyzing energy efficiency and area efficiency for different octave sizes.

Simulation Analysis on the Compression Property of Sandwich Composite (샌드위치 복합재료의 압축 특성에 관한 시뮬레이션 해석)

  • Bang, Seung-Ok;Kook, Jeong-Han;Kim, Sei-Hwan;Cho, Jae-Ung
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.13 no.2
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    • pp.478-484
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    • 2012
  • In this study, compression analyses of sandwich composites with porous core were carried out. Finite element models of aluminum foam and honeycomb core sandwich composite material were applied solid element. In the case of aluminum foam core, valid equivalence damage model was applied. In the in-plane compression analysis, the maximum load of aluminum foam core sandwich was similar with that of aluminum honeycomb core sandwich. But in case of aluminum honeycomb core sandwich, the load support region becomes longer in comparison with aluminum foam core sandwich. In the out-plane compression analysis, compression maximum load of aluminum honeycomb core sandwich was higher than that of aluminum foam core sandwich. Through these Simulation analysis, obtains the behavior of sandwich composites.

An Efficient SoC Test Architecture for Testing Various Cores in Parallel (다양한 코어의 병렬 테스트를 지원하는 효과적인 SOC 테스트 구조)

  • Kim, Hyun-Sik;Kim, Yong-Joon;Park, Hyun-Tae;Kang, Sung-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.10 s.352
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    • pp.140-150
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    • 2006
  • In this paper, we present a new hardware architecture for testing various cores embedded in SoC. The conventional solutions need much testing time since only one core is tested at single test period. To enhance this, S-TAM, a novel test architecture, and its controller which enable parallel testing of various cores are proposed. S-TAM supports bus sharing to broadcast testing and cores to be tested are selected by using it. In addition, S-TAM controller enables the effective SoC test by simultaneous controlling the various test cores which are based on the different test architectures like IEEE 1149.1 and IEEE 1500.

A Hardware Design of Ultra-Lightweight Block Cipher Algorithm PRESENT for IoT Applications (IoT 응용을 위한 초경량 블록 암호 알고리듬 PRESENT의 하드웨어 설계)

  • Cho, Wook-Lae;Kim, Ki-Bbeum;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.7
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    • pp.1296-1302
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    • 2016
  • A hardware implementation of ultra-lightweight block cipher algorithm PRESENT that was specified as a block cipher standard for lightweight cryptography ISO/IEC 29192-2 is described in this paper. Two types of crypto-core that support master key size of 80-bit are designed, one is for encryption-only function, and the other is for encryption and decryption functions. The designed PR80 crypto-cores implement the basic cipher mode of operation ECB (electronic code book), and it can process consecutive blocks of plaintext/ciphertext without reloading master key. The PR80 crypto-cores were designed in soft IP with Verilog HDL, and they were verified using Virtex5 FPGA device. The synthesis results using 0.18μm CMOS cell library show that the encryption-only core has 2,990 GE and the encryption/decryption core has 3,687 GE, so they are very suitable for IoT security applications requiring small gate count. The estimated maximum clock frequency is 500 MHz for the encryption-only core and 444 MHz for the encryption/decryption core.

A Study on the Coolant leaks Prevention Design of Heaters for Combat Vehicles (전투차량용 온수히터 냉각수 누수방지 설계에 관한 연구)

  • Park, Dong Min;Kwak, Daehwan;Jang, Jongwan
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.21 no.10
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    • pp.379-385
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    • 2020
  • This paper presents a design for preventing coolant leaks in the core part of a heater mounted in a combat vehicle. The heater is a device that makes heated coolant flow through the heater core in the crew room. A problem with coolant leaks in the heater core area during the operation of a combat vehicle was identified. This problem is caused mainly by high pressure at the junction of the tank and tube due to the vulnerability of this area. To solve this problem, an improved core was made by improving the welding method and changing the end region of the heater core to a structure that can withstand high pressure. When pressure was applied sequentially to the existing core and improved core, a leak occurred at 7.0 kgf/㎠ in the existing core while the improved core maintained its structure up to 17.0 kgf/㎠, highlighting the improvement. Finally, performance tests and environment tests were conducted to demonstrate the suitability of the improved structure. The improved heater will be applied to combat vehicles. This paper is expected to serve as a reference for improving defense capabilities by securing reliability as well as the design and analysis of failures of similar equipment.nse capabilities through securing reliability as well as the design and analysis of failures of similar equipment.