• Journal of Power Electronics
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• v.13 no.4
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• pp.729-736
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• 2013

Knowledge of a power semiconductor's operating temperature is important in circuit design and converter control. Designing appropriate circuitry that does not affect regular circuit operation during virtual junction temperature measurement at actual operating conditions is a demanding task for engineers. The proposed method enables virtual junction temperature estimation with a dedicated modified gate driver circuit based on real-time measurement of a semiconductor's quasi-threshold voltage. A simulation was conducted before the circuit was designed to verify the concept and to determine the basic properties and potential drawbacks of the proposed method.

• Progress in Superconductivity
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• v.3 no.1
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• pp.65-69
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• 2001

We measured the transport properties of$ YBa_2$$Cu_3$$O_{x}$ ramp-edge junction fabricated with interface-engineered barrier. The current-voltage characteristics show a typical resistively-shunted junction like behavior Voltage noise measurement revealed that the main source of the 1/f noise is the critical current and resistance fluctuations. The analysis of the noise data showed that the critical current fluctuations increase with temperature, whereas the resistance fluctuations are almost constant, and both fluctuations are almost correlated. The smaller magnitude of the critical current and resistance fluctuations seems to result from the columnar-deflects.s.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.864-867
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• 2003

Since the development of semiconductors, various related research has been conducted. During research, silicon diodes have been commonly used because of their simplicity and low cost in the manufacturing process. This research deals with p-n junction threshold voltages from silicon diodes due to transport current at a cryogenic temperature. At a cryogenic temperature(77K) we could get minimum current which junction threshold voltage becomes constant. This is experimented on GPIB communication and it consist of programmable current source, multimeter which gauge the threshold voltage in a very low temperature caused by transport current from 5nA to 1mA and $LN_2$(77K) for coolant. This experiment is programmed all process using Measurement studio(Lab window) tool.

• Korean Journal of Materials Research
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• v.13 no.6
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• pp.398-403
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• 2003

Shallow $p^{＋}$ n junction was formed using a ULE(ultra low energy) implanter. Deactivation phenomena were investigated for the shallow source/drain junction based on measurements of post-annealing time and temperature following the rapid thermal annealing(RTA) treatments. We found that deactivation kinetics has two regimes such that the amount of deactivation increases exponentially with annealing temperature up to $850^{\circ}C$ and that it decreases linearly with the annealing temperature beyond that temperature. We believe that the first regime is kinetically limited while the second one is thermodynamically limited. We also observed "transient enhanced deactivation", an anomalous increase in sheet resistance during the early stage of annealing at temperatures higher than X$/^{\circ}C$. Activation energy for transient enhanced deactivation was measured to be 1.75-1.87 eV range, while that for normal deactivation was found to be between 3.49-3.69 eV.

• Journal of the Korean institute of surface engineering
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• v.54 no.5
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• pp.207-212
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• 2021

The mechanical and electrical characteristics can be improved in 3D stacked IC technology which can accomplish the ultra-high integration by stacking more semiconductor chips within the limited package area through the Cu direct bonding method minimizing the performance degradation to the bonding surface to the inorganic compound or the oxide film etc. The surface was treated in a ultrasonic washer using a diamond abrasive to remove other component substances from the prepared cast plate substrate surface. FE-SEM was used to analyze the bonding characteristics of the bonded copper substrates, and the cross section of the bonded Cu conjugates at the sintering junction temperature of 100 ℃, 150 ℃, 200 ℃, 350 ℃ and the pressure of 2303 N/cm² and 3087 N/cm². At 2303 N/cm², the good bonding of copper substrate was confirmed at 350 ℃, and at the increased pressure of 3087 N/cm², the bonding condition of Cu was confirmed at low temperature junction temperature of 200 ℃. However, the recrystallization of Cu particles was observed due to increased pressure of 3087 N/cm² and diffusion of Cu atoms at high temperature of 350 ℃, which can lead to degradation in semiconductor manufacturing.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.59-65
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• 2012

A study on the electrical characteristic analysis of solar cell diodes under experimental conditions of varying temperature and frequency has been conducted. From the current-voltage (I-V) measurements, at the room temperature, we obtained the ideality factor (n) for Space Charge Region (SCR) and Quasi-Neutral Region (QNR) of 3.02 and 1.76, respectively. Characteristics showed that the value of n (at SCR) decreases with rising temperature and n (at QNR) increases with the same conditions. These are due to not only the sharply increased SCR current flow but the activated carrier recombination in the bulk region caused by defects such as contamination, dangling bonds. In addition, from the I-V measurements implemented to confirm the junction uniformity of cells, the average current dispersion was 40.87% and 10.59% at the region of SCR and QNR, respectively. These phenomena were caused by the pyramidal textured junction structure formed to improve the light absorption on the device's front surface, and these affect to the total diode current flow. These defect and textured junction structure will be causes that solar cell diodes have non-ideal electrical characteristics compared with general p-n junction diodes. Also, through the capacitance-voltage (C-V) measurements under the frequency of 180 kHz, we confirmed that the value of built-in potential is 0.63 V.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.160-160
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• 2016

In this study, we applied the low temperature curing Ag paste to replace PVD System. The electrode formation of low temperature curing Ag paste for silicon Hetero-junction solar cells is important for improving device characteristics such as adhesion, contact resistance, fill factor and conversion efficiency. The low temperature curing Ag paste is composed various additives such as solvent, various organic materials, polymer, and binder. it depends on the curing temperature conditions. The adhesion of the low temperature curing Ag paste was decided by scratch test. The specific contact resistance was measured using the transmission line method. All of the Ag electrodes were experimented at various curing temperatures within the temperature range of $160^{\circ}C-240^{\circ}C$, at $20^{\circ}C$ intervals. The curing time was also changed by varying the conditions of 10-50min. In the optimum curing temperature $200^{\circ}C$ and for 20 min, the measured contact resistance is $19.61m{\Omega}cm^2$. Over temperature $240^{\circ}C$, confirmed bad contact characteristic. We obtained photovoltaic parameter of the industrial size such as Fill Factor (FF), current density (Jsc), open-circuit voltage (Voc) and convert efficiency of up to 76.2%, 38.1 mA/cm2, 646 mV and 18.3%, respectively.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.06a
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• pp.105-106
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• 2008

• Proceedings of the Korean Institute of Building Construction Conference
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• 2005.05a
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• pp.179-183
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• 2005

In apply roof waterproof system using of synthetic high polymer sheet for rooftop measure physical performance (tension$\cdot$tearing ability, temperature relativity, heating stretch performance, junction performance, wind resistance test) by various test environment condition waterproof test of structure and performance of construction work aspect, present suitable form of construction work under these environment. Also, wish to improve durability of concrete structure as that examine in priority about adhesion method and joint junction method with waterproof out surface, and present new direction about roof system application of waterproofing method for rooftop.

• Journal of IKEEE
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• v.17 no.3
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• pp.360-364
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• 2013

The maximum breakdown voltage's characteristic within the Super Junction MOSFET structure comes from N-Drift and P-Pillar's charge balance. By developing P-Pillar from Planar MOSFET, it was confirmed that the breakdown voltage is improved through charge balance, and by setting the gate voltage at 10V, the characteristic comparisons of Planar MOSFET and Super Junction MOSFET are shown in picture 6. The results show that it had the same breakdown voltage as Planar MOSFET which increased temperature resistance by 87.4% at $.019{\Omega}cm^2$ which shows that by the temperature resistance increasing, the power module's power dissipation improved.