• 제목/요약/키워드: ion chip

검색결과 83건 처리시간 0.036초

Method of Ga removal from a specimen on a microelectromechanical system-based chip for in-situ transmission electron microscopy

  • Yena Kwon;Byeong-Seon An;Yeon-Ju Shin;Cheol-Woong Yang
    • Applied Microscopy
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    • 제50권
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    • pp.22.1-22.6
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    • 2020
  • In-situ transmission electron microscopy (TEM) holders that employ a chip-type specimen stage have been widely utilized in recent years. The specimen on the microelectromechanical system (MEMS)-based chip is commonly prepared by focused ion beam (FIB) milling and ex-situ lift-out (EXLO). However, the FIB-milled thin-foil specimens are inevitably contaminated with Ga+ ions. When these specimens are heated for real time observation, the Ga+ ions influence the reaction or aggregate in the protection layer. An effective method of removing the Ga residue by Ar+ ion milling within FIB system was explored in this study. However, the Ga residue remained in the thin-foil specimen that was extracted by EXLO from the trench after the conduct of Ar+ ion milling. To address this drawback, the thin-foil specimen was attached to an FIB lift-out grid, subjected to Ar+ ion milling, and subsequently transferred to an MEMS-based chip by EXLO. The removal of the Ga residue was confirmed by energy dispersive spectroscopy.

기판접합기술을 이용한 MEMS 컨덴서 마이크로폰의 설계와 제작 (Design and Fabrication of MEMS Condenser Microphone Using Wafer Bonding Technology)

  • 권휴상;이광철
    • 한국소음진동공학회논문집
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    • 제16권12호
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    • pp.1272-1278
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    • 2006
  • This paper presents a novel MEMS condenser microphone with rigid backplate to enhance acoustic characteristics. The MEMS condenser microphone consists of membrane and backplate chips which are bonded together by gold-tin(Au/Sn) eutectic solder bonding. The membrane chip has $2.5mm{\times}2.5mm$, 0.5${\mu}m$ thick low stress silicon nitride membrane, $2mm{\times}2mm$ Au/Ni/Cr membrane electrode, and 3${\mu}m$ thick Au/Sn layer. The backplate chip has $2mm{\times}2mm$, 150${\mu}m$ thick single crystal silicon rigid backplate, $1.8mm{\times}1.8mm$ backplate electrode, and air gap, which is fabricated by bulk micromachining and silicon deep reactive ion etching. Slots and $50{\sim}60{\mu}m$ radius circular acoustic holes to reduce air damping are also formed in the backplate chip. The fabricated microphone sensitivity is 39.8 ${\mu}V/Pa$(-88 dB re. 1 V/Pa) at 1 kHz and 28 V polarization voltage. The microphone shows flat frequency response within 1 dB between 20 Hz and 5 kHz.

A Low-Power Single Chip Li-Ion Battery Protection IC

  • Lee, Seunghyeong;Jeong, Yongjae;Song, Yungwi;Kim, Jongsun
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제15권4호
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    • pp.445-453
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    • 2015
  • A fully integrated cost-effective and low-power single chip Lithium-Ion (Li-Ion) battery protection IC (BPIC) for portable devices is presented. The control unit of the battery protection system and the MOSFET switches are integrated in a single package to protect the battery from over-charge, over-discharge, and over-current. The proposed BPIC enters into low-power standby mode when the battery becomes over-discharged. A new auto release function (ARF) is adopted to release the BPIC from standby mode and safely return it to normal operation mode. A new delay shorten mode (DSM) is also proposed to reduce the test time without increasing pin counts. The BPIC implemented in a $0.18-{\mu}m$ CMOS process occupies an area of $750{\mu}m{\times}610{\mu}m$. With DSM enabled, the measured test time is dramatically reduced from 56.82 s to 0.15 s. The BPIC chip consumes $3{\mu}A$ under normal operating conditions and $0.45{\mu}A$ under standby mode.

Heavy-Ion Radiation Characteristics of DDR2 Synchronous Dynamic Random Access Memory Fabricated in 56 nm Technology

  • Ryu, Kwang-Sun;Park, Mi-Young;Chae, Jang-Soo;Lee, In;Uchihori, Yukio;Kitamura, Hisashi;Takashima, Takeshi
    • Journal of Astronomy and Space Sciences
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    • 제29권3호
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    • pp.315-320
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    • 2012
  • We developed a mass-memory chip by staking 1 Gbit double data rate 2 (DDR2) synchronous dynamic random access memory (SDRAM) memory core up to 4 Gbit storage for future satellite missions which require large storage for data collected during the mission execution. To investigate the resistance of the chip to the space radiation environment, we have performed heavy-ion-driven single event experiments using Heavy Ion Medical Accelerator in Chiba medium energy beam line. The radiation characteristics are presented for the DDR2 SDRAM (K4T1G164QE) fabricated in 56 nm technology. The statistical analyses and comparisons of the characteristics of chips fabricated with previous technologies are presented. The cross-section values for various single event categories were derived up to ~80 $MeVcm^2/mg$. Our comparison of the DDR2 SDRAM, which was fabricated in 56 nm technology node, with previous technologies, implies that the increased degree of integration causes the memory chip to become vulnerable to single-event functional interrupt, but resistant to single-event latch-up.

Ion Chip과 황토 처리가 콩나물의 생육 및 물리화학적 특성에 미치는 영향 (Effect of ion Chip and Yellow Soil on Growth and Physicochemical Characteristics of Soybean Sprouts)

  • 김인숙;최선영;정미자;김태훈;성낙주
    • 한국식품영양학회지
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    • 제18권4호
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    • pp.316-324
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    • 2005
  • 본 실험의 목적은 콩나물의 생육 특성 및 물리화학적 변화에 ion chip과 황토가 미치는 영향을 알아보았다. 콩나물의 무게와 길이는 4일까지 급격히 생장하였으나, 그 후 완만한 속도로 생장하였다. 총 비타민 C의 함량은 이온수(I.W), 수돗물과 이온수에 황토 $1.0\%$를 첨가한 군(T.W+l.0, I.W+l.0)에서 6일 이후 급격하게 증가하였다. 콩나물에 함유된 미네랄 중 Mg, Ca, K, Fe의 함량이 다른 미네랄보다 높았다. 철의 함량은 이온수에 황토 $1.0\%$를 첨가한 군(I.W+l.0)에서 가장 높게 검출되었다. 이온수로 4일 동안 재배한 콩나물에 함유된 glutamic acid는 수도수에 비해 높게 나타났다. 핵산관련 물질은 UMP, CMP, AMP 및 Hx이 검출되었는데, UMP가 가장 높았다. 유리당은 sucrose, raffinose, stachyose가 검출되었고, sucrose가 그 중에 가장 높은 함량이었다.

기판접합기술을 이용한 두꺼운 백플레이트와 수직음향구멍을 갖는 정전용량형 마이크로폰의 설계와 제작 (Design and fabrication of condenser microphone with rigid backplate and vertical acoustic holes using DRIE and wafer bonding technology)

  • 권휴상;이광철
    • 센서학회지
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    • 제16권1호
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    • pp.62-67
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    • 2007
  • This paper presents a novel MEMS condenser microphone with rigid backplate to enhance acoustic characteristics. The MEMS condenser microphone consists of membrane and backplate chips which are bonded together by gold-tin (Au/Sn) eutectic solder bonding. The membrane chip has 2.5 mm${\times}$2.5 mm, $0.5{\mu}m$ thick low stress silicon nitride membrane, 2 mm${\times}$2 mm Au/Ni/Cr membrane electrode, and $3{\mu}m$ thick Au/Sn layer. The backplate chip has 2 mm${\times}$2 mm, $150{\mu}m$ thick single crystal silicon rigid backplate, 1.8 mm${\times}$1.8 mm backplate electrode, and air gap, which is fabricated by bulk micromachining and silicon deep reactive ion etching. Slots and $50-60{\mu}m$ radius circular acoustic holes to reduce air damping are also formed in the backplate chip. The fabricated microphone sensitivity is $39.8{\mu}V/Pa$ (-88 dB re. 1 V/Pa) at 1 kHz and 28 V polarization voltage. The microphone shows flat frequency response within 1 dB between 20 Hz and 5 kHz.

교정용 장치물에 대한 TiN Ion Plating의 응용 (APPLICATION OF TIN ION-PLATING TO THE ORTHODONTIC APPLIANCE)

  • 권오원;김교한
    • 대한치과교정학회지
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    • 제21권1호
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    • pp.7-16
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    • 1991
  • To estimate the possibility of the application of TiN ion-plating to the orthodontic appliance, colorimetric properties, and characteristics of ion-plated film as well as adhesive strength of TiN film to the substrate and mechanical properties of ion-plated orthodontic appliance were investigated. The obtained results were as follows: 1) TiN ion-plated film had the colorimetric properties which were the hue of about 2.5 Y, the brightness of about 6, and the chroma of about 4 by the standard color chip of JIS. 2) TiN ion-plated film was $2{\mu}m$ in thickness and its deposition pattern was rather irregular. 3) TiN phase was confirmed on the X-ray diffraction pattern. 4) Critical load for delamination of ion-plated film from stainless steel band was 10N. 5) Tensile and yield strength of ion-plated specimen was increased about 10Kg $f/mm^2$, while elongation was decreased $1\%$ compairing to the values of the non ion-plated specimen.

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저 에너지 이온 주입의 개선을 위한 변형된 감속모드 이온 주입의 안정화 특성 (Stabilization of Modified Deceleration Mode for Improvement of Low-energy Ion Implantation Process)

  • 서용진;박창준;김상용
    • 한국전기전자재료학회논문지
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    • 제16권3호
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    • pp.175-180
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    • 2003
  • As the integrated circuit device shrinks to the deep submicron regime, the ion implantation process with high ion dose has been attracted beyond the conventional ion implantation technology. In particular, for the case of boron ion implantation with low energy and high dose, the stabilization and throughput of semiconductor chip manufacturing are decreasing because of trouble due to the machine conditions and beam turning of ion implanter system. In this paper, we focused to the improved characteristics of processing conditions of ion implantation equipment through the modified deceleration mode. Thus, our modified recipe with low energy and high ion dose can be directly apply in the semiconductor manufacturing process without any degradation of stability and throughput.

마이크로펌프를 이용한 PCR Chip의 구동 (Operation of PCR chip by micropump)

  • 최종필;반준호;장인배;김헌영;김병희
    • 한국공작기계학회:학술대회논문집
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    • 한국공작기계학회 2004년도 추계학술대회 논문집
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    • pp.463-467
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    • 2004
  • This paper presents the fabrication possibility of the micro actuator which uses a micro-thermal bubble, generated b micro-heater under pulse heating. The valve-less micropump using the diffuser/nozzle is consists of the lower plate, he middle plate, the upper plate. The lower plate includes the channel and chamber are fabricated on high processability silicon wafer by the DRIE(Deep Reactive Ion Etching) process. The middle plate includes the chamber and diaphragm d the upper plate is the micro-heater. The Micropump is fabricated by bonding process of the three layer. This paper resented the possibility of the PCR chip operation by the fabricated micropump.

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RTP Anneal과 추가 이온주입에 의한 저-저항 텅스텐 bit-line 구현 (Low-Resistance W Bit-line Implementation with RTP Anneal & Additional Ion Implantation.)

  • 이용희;우경환;최영규;류기한;이천희
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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    • pp.266-269
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    • 2000
  • As the device geometry continuously shrink down less than sub-quarter micrometer, DRAM makers are going to replace conventional tungsten-polycide with tungsten bit-line structure in order to reduce the chip size and use it as a local interconnection. In this paper we showed low resistance and leakage tungsten bit-line process with various RTP(Rapid Thermal Process) temperature. As a result we obtained that major parameters impact on tungsten bit-line process are RTP Anneal temperature and BF2 ion implantation dopant. These tungsten bit-line process are promising to fabricate high density chip technology.

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