• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.37-42
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• 2008

In H.264/AVC decoder, intra predictor, motion compensator, and deblocking filter need to read reference images in external frame memory in decoding process. They read external frame memory very frequently, which lowers system operation speed and increases power consumption. This paper proposes a intra predictor integrated with motion compensator without external frame memory. It achieves power reduction and memory bandwidth minimization by exploiting data reuse of common and repetitive pixels. The proposed infra predictor achieves more than $45%\;{\sim}\;75%$ cycle time reduction compared with conventional intra predictors.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2503-2510
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• 2012

This paper proposes a parallel operation intra predictor for H.264/AVC decoder. In previous intra predictor design, common operation units were designed for 17 prediction modes in order to compute more effectively. However, it was designed by analyzing the equation applied to one pixel. So, there are four operation units for computing 16 pixels in a $4{\times}4$ block and they need four cycles. In this paper, the proposed intra predictor contains T3(Three Type Transform) operation unit for parallel operation. It divides 17 modes into 3 types to calculate 16 pixels of a $4{\times}4$ block in only one cycle and needs 16 cycles minimum in 16x16 block. As the result of the experiment, in terms of processing cycle, the performance of proposed intra predictor is 58.95% higher than the previous one.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.24-30
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• 2010

In this paper, we described intra prediction which is the one of techniques to be used for higher compression performance in H.264/AVC and proposed the design of intra predictor for efficient intra prediction mode processing. The proposed system is consist of processing elements, precomputation processing elements, an intra prediction controller, an internal memory and a register controller. The proposed system needs the reduced the computation cycles by using processing elements and precomputation processing element and also needs the reduced the number of access time to external memory by using internal memory and registers architecture. We designed the proposed system with Verilog-HDL and verified with suitable test vectors which are encoded YUV files. The proposed architecture belongs to the baseline profile of H.264/AVC decoder and is suitable for portable devices such as cellular phone with the size of $176{\times}144$. As a result of experiment, the performance of the proposed intra predictor is about 60% higher than that of the previous one.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.175-178
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• 2009

H.264/AVC is a video coding standard of ITU-T and ISO/IEC, and widely spreads its application due to its high compression ratio more than twice that of MPEG-2 and high image quality. In this paper, we explained Intra Prediction in H.264/AVC, which is able to achieve higher compressing efficiency from correlation removal of adjacent samples in spatial domain, and proposed efficient Intra Predictor architecture design for H.264/AVC decoder. The proposed system reduced computation cycle using processing element and precomputation processing element and also reduced the number of access to external memory using efficient register. We designed the proposed system with Verilog-HDL and verified with suitable test vector. The proposed Intra Predictor achieved about 60% cycle reduction comparing with existing Intra Predictors.

• Journal of information and communication convergence engineering
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• v.11 no.1
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• pp.50-55
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• 2013

In this paper, we propose a parallel intra-operation unit and a memory architecture for improving the performance of intra-prediction, which utilizes spatial correlation in an image to predict the blocks and contains 17 prediction modes in total. The design is targeted for portable devices applying H.264/AVC decoders. For boosting the performance of the proposed design, we adopt a parallel intra-operation unit that can achieve the prediction of 16 neighboring pixels at the same time. In the best case, it can achieve the computation of one luma $16{\times}16$ block within 16 cycles. For one luma $4{\times}4$ block, a mere one cycle is needed to finish the process of computation. Compared with the previous designs, the average cycle reduction rate is 78.01%, and the gate count is slightly reduced. The design is synthesized with the MagnaChip $0.18{mu}m$ library and can run at 125 MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.8 no.4
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• pp.156-163
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• 1983

A composite DPCM system is designed and implemented for the transmission of a NTSC color TV signal over a 44, 736Mbps channel. It is based on an intra-field fourth-order linear predictor and a nonlinear quantizer of five bits. The predictor preserves both the luminance and the chrominance components through one predictor. To accomodate the speed requirement for real time processing, mainly high speed ECL gates and memory devices are used in the hardware implementation. Experimental results show that this composite DPCM system can be applicable for a practical transmission of color TV signal with CATV quality.

• Korean Journal of Child Studies
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• v.21 no.4
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• pp.159-175
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• 2000

This study explored how communication with parents, relations with teachers and intra- and extra-mural activities were related to peer relationships. Data were collected from 453 middle school students in the city of Iksan. Results showed that students with more harmonious communication with parents reported more desirable peer relationships. More familiar and friendly relations with teachers was also associated with more harmonious peer relationships. As adolescents appeared more vigorous in intra- and extra-mural activities, they had friendlier peer relationships. Gender, communication with fathers, relations with teachers, and intra- and extra-mural activities had significant effects on peer relationships. Relations with teachers was the best predictor for peer relationships.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.4
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• pp.736-739
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• 2009

In this paper, an efficient lossless compression algorithm using motion adaptation is proposed. It is divided into two parts: a motion adaptation based nonlinear predictor part and a residual data coding part. The proposed nonlinear predictor can reduce prediction error by learning from its past prediction errors using motion adaption. The predictor decides the proper selection of the intra and inter prediction values according to the past prediction error. The reduced error is coded by existing context adaptive coding method. Experimental results show that the proposed algorithm has the higher compression ratio than context modeling methods, such as FELICS, CALIC, and JPEG-LS.

• The Journal of the Korea Contents Association
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• v.17 no.5
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• pp.1-7
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• 2017

Joint Collaborative Team on Video Coding (JCT-VC) of ISO/IEC MPEG and ITU-T developed the HEVC Screen Content Coding (HEVC SCC) standard as the HEVC extension for the screen content video coding. The Intra Block Copy (IBC) is the most effective tool adopted in HEVC SCC and predicts current block from already reconstructed neighboring blocks in the same picture. To reduce the amount of data in BV (Block Vector) to be transmitted, a BV predictor (BVP) is used to generate the BV differences in the IBC BV coding. In this paper, we analyze the current BV prediction process using HEVC reference software SCM-2.0 and SCM-4.0. Based on the analysis results, we propose an improved BVP candidate selection algorithm by adding a search process for adjacent BVs in addition to the existing spatial BVP candidates. Experimental results show that the BD-rate reduction of our proposed improvements ranges from 0.2% to 1%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.93-101
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• 2007

Small area and low power implementation are important requirements for various multimedia processing hardware, especially for mobile environment. This paper presents a hardware architecture of H.264/AVC Intra Prediction module aiming on small area and low power. A single arithmetic unit was shared and processed sequentially for all mode decisions and computations to predict an image frame. As a result, we could get smaller area and smaller memory size compared to other existing implementations. The proposed architecture was verified using the Altera Excalibur device, and the implemented hardware has been described in Verilog-HDL and synthesized on Samsung STD130 0.18um CMOS Standard Cell Library using Synopsys Design Compiler. The synthesis result was about 11.9K logic gates and 1078 byte internal SRAM and the maximum operating frequency was 107Mhz. It consumes 879,617 clocks to process one QCIF frame, which means it can process 121.5 QCIF$(176\times144)$ frames per second, therefore it shows that it can be used for real time H.264/AVC encoding of various multimedia applications.