• Journal of the Korean Geotechnical Society
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• v.38 no.10
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• pp.17-29
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• 2022

Recently, the interest in integrated underground geospatial information mapping (IUGIM) to ensure the safety of underground spaces and facilities has been increasing. Because IUGIM is used in the fields of underground space development and underground safety management, the up-to-dateness and accuracy of information are critical. In this study, IUGIM and field data were classified, and the accuracy of IUGIM was improved by spatial interpolation. A spatial interpolation technique was used to process borehole data in IUGIM, and a quantitative evaluation was performed with mean absolute error and root mean square error through the cross-validation of seven interpolation results according to the technique and model. From the cross-validation results, accuracy decreased in the order of nonuniform rational B-spline, Kriging, and inverse distance weighting. In the case of Kriging, the accuracy difference according to the variogram model was insignificant, and Kriging using the spherical variogram exhibited the best accuracy.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.10
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• pp.15-23
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• 2016

To support the telematics and infotainment services, vehicle-to-everything (V2X) communication requires a robust and reliable network. To do this, the 3rd Generation Partnership Project (3GPP) has recently developed V2X communication. For reliable communication, accurate channel estimation should be done. However, because vehicle speed is very fast, radio channel is rapidly changed with time. Therefore, it is difficult to accurately estimate the channel. In this paper, we propose the new linear minimum mean square error (LMMSE) channel interpolation scheme based on the Long Term Evolution (LTE) sidelink system in vehicle-to-vehicle (V2V) environments. In our proposed reduced decision error (RDE) channel estimation scheme, LMMSE channel estimation is applied in the pilot symbol, and then in the data symbol, smoothing and LMMSE channel interpolation scheme is applied. After that, time and frequency domain averaging are applied to obtain the whole channel frequency response. In addition, the LMMSE equalizer of the receiver side can reduce the error propagation due to the decision error. Therefore, it is possible to detect the reliable data. Analysis and simulation results demonstrate that the proposed scheme outperforms currently conventional schemes in normalized mean square error (NMSE) and bit error rate (BER).

• Journal of the Korean association of regional geographers
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• v.10 no.2
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• pp.389-406
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• 2004

with the increasing popularity of regional studies, the importance of regional data has been recognized dramatically in recent years. However, due to potential problems from the intrinsic characteristics of aggregate regional data for the research, and incompatible regional units between source and target regional data units, the method for reorganizing the regional data units for a given research analysis should be required. In this regard, the purpose of this research is to review the significant interpolation methods for reorganizing the data units and, based on it, to propose the population weighted interpolation method. For the first purpose, areal weighted interpolation method, pycnophylactic method, dasymetric method, area-to-point method were reviewed. The proposed population-weighted interpolation method was applied to the case study of population census regional data in Erie County, NY, compared with areal weighted interpolation method, pycnophylactic method in terms of several statistical characteristics.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.14-23
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• 2011

In this paper, a 7-bit 2GSPS folding/interpolation A/D Converter(ADC) with a Self-Calibrated Vector Generator is proposed. The ADC structure is based on a folding/interpolation architecture whose folding/interpolation rate is 4 and 8, respectively. A cascaded preprocessing block is not only used in order to drive the high input signal frequency, but the resistive interpolation is also used to reduce the power consumption. Based on a novel self-calibrated vector generator, further, offset errors due to device mismatch, parasitic resistors. and parasitic capacitance can be reduced. The chip has been fabricated with a 1.2V 0.13um 1-poly 7-metal CMOS technology. The effective chip area including the calibration circuit is 2.5$mm^2$. SNDR is about 39.49dB when the input frequency is 9MHz at 2GHz sampling frequency. The SNDR is improved by 3dB with the calibration circuit.

• Wind and Structures
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• v.5 no.2_3_4
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• pp.301-316
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• 2002

An important goal of computational wind engineering is to impact the design process with simulations of flow around buildings and bridges. One challenging aspect of this goal is to solve the Navier-Stokes (NS) equations accurately. For the unsteady computations, an adaptive finite element technique may reduce the computer time and storage. The preliminary application of a p-version as well as an h-version adaptive technique to computational wind engineering has been reported in previous paper. The details on the implementation of p-adaptive technique will be discussed in this paper. In this technique, two posteriori error estimations, which are based on the velocity and vorticity, are first presented. Then, the polynomial order of the interpolation function is increased continuously element by element until the estimated error is less than the accepted. The second through sixth orders of hierarchical functions are used as the interpolation polynomials. Unequal order interpolations are used for velocity and pressure. Using the flow around a circular cylinder with Reynolds number of 1000 the two error estimators are compared. The result show that the estimated error based on the velocity is lower than that based on the vorticity.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.1-9
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• 2012

A 10-b 500 MS/s A/D converter (ADC) with a hybrid calibration and error correction logic is described. The ADC employs a single-channel cascaded folding-interpolating architecture whose folding rate (FR) is 25 and interpolation rate (IR) is 8. To overcome the disadvantage of an offset error, we propose a hybrid self-calibration circuit at the open-loop amplifier. Further, a novel prevision digital error correction logic (DCL) for the folding ADC is also proposed. The ADC prototype using a 130 nm 1P6M CMOS has a DNL of ${\pm}0.8$ LSB and an INL of ${\pm}1.0$ LSB. The measured SNDR is 52.34-dB and SFDR is 62.04-dBc when the input frequency is 78.15 MHz at 500 MS/s conversion rate. The SNDR of the ADC is 7-dB higher than the same circuit without the proposed calibration. The effective chip area is $1.55mm^2$, and the power dissipates 300 mW including peripheral circuits, at a 1.2/1.5 V power supply.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.28 no.3
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• pp.271-280
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• 2004

Assessment of image registration for Pressure Sensitive Paint (PSP) was performed. A 16 bit camera and LED lamp were used with Uni-FIB paint (ISSI). Because of model displacement and deformation at 'wind-on' condition, a large error of the intensity ratio was induced between 'wind-on' and' wind-off images. To correct the error, many kinds of image registrations were tested. At first, control points were marked on the model surface to find the coefficients of polynomial transform functions between the 'wind-off' 'wind-on' images. The 2nd-order polynomial function was sufficient for representing the model displacement and deformation. An automatic detection scheme was introduced to find the exact coordinates of the control points. The present automatic detection algorithm showed more accurate and user-friendly than the manual detection algorithm. Since the coordinates of transformed pixel were not integer, five interpolation methods were applied to get the exact pixel intensity after transforming the 'wind-on' image. Among these methods, the cubic convolution interpolation scheme gave the best result.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.4
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• pp.690-696
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• 2006

This study applies the methods proposed in this issue[1] to the 11 rainfall gauging stations of the Pyongchang area. Also, this study analyzes the error range of each interpolation method, and considers spatial distribution according to the number of gauging station. As the results, the linear programming methods shows the best minimum error. However, this method might be difficult to apply in the field because of need for programming. Comparatively, the inverse distance method shows more simple and accurate results than the linear programming one. The result of this study could contribute to the increase of accuracy for the filling of missing rainfall data.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.59-67
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• 2013

Reed-Solomon (RS) codes are powerful error-correcting codes used in diverse applications. Recently, algebraic soft-decision decoding algorithm for RS codes that can correct the errors beyond the error correcting bound has been proposed. The algorithm requires very intensive computations for interpolation, therefore an efficient VLSI architecture, which is realizable in hardware with a moderate hardware complexity, is mandatory for various applications. In this paper, we propose an efficient architecture with low hardware complexity for interpolation in soft-decision list decoding of Reed-Solomon codes. The proposed architecture processes the candidate polynomial in such a way that the terms of X degrees are processed in serial and the terms of Y degrees are processed in parallel. The processing order of candidate polynomials adaptively changes to increase the efficiency of memory access for coefficients; this minimizes the internal registers and the number of memory accesses and simplifies the memory structure by combining and storing data in memory. Also, the proposed architecture shows high hardware efficiency, since each module is balanced in terms of latency and the modules are maximally overlapped in schedule. The proposed interpolation architecture for the (255, 239) RS list decoder is designed and synthesized using the DongbuHitek $0.18{\mu}m$ standard cell library, the number of gate counts is 25.1K and the maximum operating frequency is 200 MHz.

• Proceedings of the IEEK Conference
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• 2001.06d
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• pp.65-68
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• 2001

In this paper, we propose a method to interpolate two images obtained from two parallel cameras. The proposed method uses BDM(Bidirectional Disparity Map) to prevent hole generation due to occlusion. Furthermore, we use the block-based DM(Disparity Map) to decrease the amount of computation, and also use the adaptive block size to minimize the error of the block-based DM.