• Title/Summary/Keyword: interleaving

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Blocking Effect Reduction in JPEG Image using Interleaving DCT (Interleaving DCT를 이용한 JPEG 이미지의 블록킹 현상 감소)

  • 하근희;김도년;조동섭
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 1998.03a
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    • pp.153-156
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    • 1998
  • JPEG은 정지 영상의 압축 표준으로 8$\times$8 블록을 기반으로 DCT 변환을 한 후 양자화 및 엔트로피 부호화 과정을 통해 압축이 이루어진다. DCT는 이미지를 공간 영역에서 주파수 영역으로 변환하는 기법으로 대체로 저주파 성분은 저주파 성분끼리, 고주파 성분은 고주파 성분끼리 모아준다. 이러한 형태는 필요 없는 성분들을 쉽게 제거할 수 있어 압축이 효율적으로 이루어지도록 한다. 블록 기반의 압축 기법을 적용할 때 흔히 나타나는 문제점은 블록 기반으로 인해 발생하는 블?킹 현상으로서 이는 양자화로 인한 정보의 손실에서 비롯되며 그 기본이 되는 8$\times$8 블록 단위로 나타난다. 본 연구세어서는 작은 블록 단위를 16$\times$16의 매크로블록으로 확대한 개념을 이용하여 매크로 블록 내의 수직 및 수평 방향으로 1:2단위로 샘플링한 4개의 8$\times$8블록 간의 블록킹 경계로 없애 주도록 하고자 한다. 또한 16$\times$16의 DCT 블록 대신 16$\times$16 블록내의 8$\times$8 블록들을 이용함으로써 표준 기법에서 이용되는 8$\times$8 단위의 양자화 테이블이나 RLE기법 등을 그대로 적용할 수 있다.

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Error Performance Analysis of a FEC for the Cable Modem (유선 케이블 모뎀의 FEC 성능평가)

  • 이창재;김경덕;최형진
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.26 no.11A
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    • pp.1803-1811
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    • 2001
  • In this paper, Forward Error Correction(FEC) that is satisfied with ITU-T Recommendation J.83, Annex B(North American Data Over Cable Service Interface Specifications(DOCSIS) for Multimedia Cable Network System(MCNS)) is analyzed. The FEC consist of Reed-Solomon(RS) layer, interleaving layer, randomization layer, and trellis coded modulation(TCM) layer. The effects of quantization of input symbol and of trace-back depth in the Viterbi decoder are simulated over AWGN channels.

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Study on 36-pulse Back-to-Back Voltage Source Converter with Pulse-Interleaving Auxiliary Circuit for HVDC Application (펄스다중화 보조회로를 이용한 36-펄스 Back-to-Back 전압원 컨버터의 직류송전 적용연구)

  • Baek, Seung-Taek;Choi, Jun-Young;Han, Byung-Moon
    • The Transactions of the Korean Institute of Electrical Engineers A
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    • v.55 no.3
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    • pp.102-108
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    • 2006
  • This paper proposes a 36-pulse back-to-back voltage source converter using four sets of 12-pulse bridges with pulse-Interleaving auxiliary circuit. The proposed back-to-back voltage source converter has an independent control capability of active power and reactive power at the at connection point. The principle of increasing the number of pulses was analyzed using theoretical approach. The operational feasibility of proposed system was verified through computer simulations with PSCAD/EMTDC software. The proposed back-to-back converter can be widely used for the HVDC and FACTS devices.

A Study of Interleaved AC/DC Converter to Improved Power Factor and Current Ripple (역률과 전류 리플을 개선한 인터리브 AC/DC 컨버터에 관한 연구)

  • Seo, Sang-Hwa;Kim, Yong;Kwon, Soon-Do;Bae, Jin-Yong;Eom, Tae-Min
    • Proceedings of the KIEE Conference
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    • 2009.04b
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    • pp.152-155
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    • 2009
  • In high power application, PFC(Power Factor Correction) pre-regulators are generally required. PFC pre-regulators could achieve unity power factor, reduce line input current harmonics and utilize full line power. Interleaving PFC converters could reduce input ripple current, output capacitor ripple current and inductor size. With this closed loop interleaving method, both two phase converters are working at the boundary between continuous and discontinuous mode and accurate 180 degree phase shift is achieved. Implementation of this strategy could be easily integrated to the control chip. Finally, experimental results of a two-phase interleaved boost PFC are presented to verify the discussed features.

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New Configuration of 36-pulse Voltage Source Converter Using Pulse-Interleaving Auxiliary Bridge Circuit (펄스다중화 보조브리지회로를 이용한 새로운 구조의 36-펄스 전압원 컨버터)

  • Han, B.M.;Baek, S.T.;Jon, Y.S.
    • Proceedings of the KIEE Conference
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    • 2004.11b
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    • pp.31-35
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    • 2004
  • This paper proposes a new configuration of 36-pulse voltage source converter which consists of two 6-pulse bridges and a pulse-interleaving auxiliary circuit. The system topology of proposed converter was derived to increase the pulse number of converter output voltage without increasing the number of 6-pulse bridges. The gate pulse generation was analyzed using the theoretical approach of multi-pulse switching converter. The operational feasibility of proposed system was verified by computer simulations with PSCAD/TMTDC software and experimental works with 3kVA hardware prototype. The proposed converter can be widely used for the uninterruptible power supply, the power quality compensator, and the distributed power generation, such as solar and fuel fell power system.

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Digitally Controlled Interleaving Tapped-Inductor Boost Converter for Photovoltaic Module Integrated Converters (PV MIC)

  • Lee, Jye-June;Kim, Jitae;Bae, Hyunsu;Cho, B.H.
    • Proceedings of the KIPE Conference
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    • 2010.11a
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    • pp.74-75
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    • 2010
  • As global warming due to burning fossil fuels and natural resource depletion issues have emerged, the development of renewable energy sources such as photovoltaics (PV) has been brought to recent interest. Amongst the vast efforts to harvest and convert solar energy into electricity, the module integrated converters (MIC) has become a worthy topic of research for grid-connected photovoltaic systems. Due to the required high-boosting qualities, only a restricted amount of DC/DC converter topologies can be applied to MICs. This paper investigates the possibility of a tapped-inductor boost converter as a candidate for PV MICs. A dual-inductor interleaving scheme operating slightly above the boundary of the two conduction modes (BCM) is suggested for reduction of input current ripple and minimization of component stress. A digital controller is used for implementation, assuring maximum power tracking and transfer while providing sufficient computational space for other grid connectivity applications, etc. For verification, a 200W converter is designed and simulated via computer software including component losses. High efficiency over a wide power range proves the feasibility of the proposed PV MIC system.

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Design of Bit Manipulation Accelerator fo Communication DSP (통신용 DSP를 위한 비트 조작 연산 가속기의 설계)

  • Jeong Sug H.;Sunwoo Myung H.
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.42 no.8 s.338
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    • pp.11-16
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    • 2005
  • This paper proposes a bit manipulation accelerator (BMA) having application specific instructions, which efficiently supports scrambling, convolutional encoding, puncturing, and interleaving. Conventional DSPs cannot effectively perform bit manipulation functions since かey have multiply accumulate (MAC) oriented data paths and word-based functions. However, the proposed accelerator can efficiently process bit manipulation functions using parallel shift and Exclusive-OR (XOR) operations and bit jnsertion/extraction operations on multiple data. The proposed BMA has been modeled by VHDL and synthesized using the SEC $0.18\mu m$ standard cell library and the gate count of the BMA is only about 1,700 gates. Performance comparisons show that the number of clock cycles can be reduced about $40\%\sim80\%$ for scrambling, convolutional encoding and interleaving compared with existing DSPs.

A Study on Video Data Protection Method based on MPEG using Dynamic Shuffling (동적 셔플링을 이용한 MPEG기반의 동영상 암호화 방법에 관한 연구)

  • Lee, Ji-Bum;Lee, Kyoung-Hak;Ko, Hyung-Hwa
    • Journal of Korea Multimedia Society
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    • v.10 no.1
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    • pp.58-65
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    • 2007
  • This dissertation proposes digital video protection algorithm lot moving image based on MPEG. Shuffling-based encryption algorithms using a fixed random shuffling table are quite simple and effective but vulnerable to the chosen plaintext attack. To overcome this problem, it is necessary to change the key used for generation of the shuffling table. However, this may pose a significant burden on the security key management system. A better approach is to generate the shuffling table based on the local feature of an image. In order to withstand the chosen plaintext attack, at first, we propose a interleaving algorithm that is adaptive to the local feature of an image. Secondly, using the multiple shuffling method which is combined interleaving with existing random shuffling method, we encrypted the DPCM processed 8*8 blocks. Experimental results showed that the proposed algorithm needs only 10% time of SEED encryption algorithm and moreover there is no overhead bit. In video sequence encryption, multiple random shuffling algorithms are used to encrypt the DC and AC coefficients of intra frame, and motion vector encryption and macroblock shuffling are used to encrypt the intra-coded macroblock in predicted frame.

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Performance Analysis of Service Model between server and client on PMSS System (PMSS 시스템에서 서버/클라이언트 간 서비스 모델의 성능분석)

  • Lee, Min-Hong;Kim, Kyung-Hoon;Nam, Ji-Seung
    • The KIPS Transactions:PartA
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    • v.11A no.3
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    • pp.207-212
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    • 2004
  • This paper provides the higher user QoS(Quality of Service) by analyzing media service model between server and client in single VoD(Video on Demand) environment and applying it to parallel VoD environment. Media service model is divided into the Client Pull, Server Push, and IPP(Interleaving Pull & Push) model. A server sends data based on client's request in the Client Pull Model. A server one-sidedly sends data without client's request in the Server Pull model. And the WP model unites above two models. For a parallel VoD environment, We built the PMSS system which provides the parallel media streaming services that one client is simultaneously served by several servers. In the single and parallel VoD environment, We compare and analyze the performance of service models with respect to network delay and data size in buffer. In this experiment, we found that IPP service model keeps the least network delay and stable client buffer in the parallel VoD environment. This result shows that PMSS can provide the more quality of service.