• Applied Microscopy
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• v.25 no.2
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• pp.65-72
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• 1995

The interfacial structures of ZnSe/GaAs which were grown by single chamber MBE at $300^{\circ}C$ were investigated by high resolution transmission electron microscope working at 300 kV with resolution of 0.18 nm. The interfaces of ZnSe/GaAs whose thickness is 2,700 nm are wavy and extensive stacking faults were formed in ZnSe epilayer but the interfaces maintained the coherency with the substrate GaAs. The stacking faults are formed in {111} planes and their sizes are $10{\sim}20nm$ in length and two or three atomic layer in width with the density of $10^9/cm^2$. Micortwins and moire fringes are also observed. However. in 10 nm ZnSe epilayer, the interfaces are pseudomorphic and only moire fringes are observed in local areas. The cylindrical defects which are perpendicular to the interface with $50{\sim}60nm$ in length, were observed with the interval of 50 nm at ZnSe/GaAs interfaces in 2,700nm epilayer. The origin and character of these defects are unknown, however, they played a role of producing the structural defects at the interfaces.

• Journal of the Korean Society for Precision Engineering
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• v.20 no.10
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• pp.183-190
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• 2003

Major device failures such as die cracking, interfacial delamination and warpage in flip chip packages are due to excessive heat and thermal gradients- There have been significant researches toward understanding the thermal performance of electronic packages, but the majority of these studies do not take into account the combined effects of thermo-mechanical interactions of the different package constituents. This paper investigates the thermo-mechanical performance of flip chip package constituents based on the finite element method with thermo-mechanically coupled elements. Delaminations with different lengths between the silicon die and underfill resin interfaces were introduced to simulate the defects induced during the assembly processes. The temperature gradient fields and the corresponding stress distributions were analyzed and the results were compared with isothermal case. Parametric studies have been conducted with varying thermal conductivities of the package components, substrate board configurations. Compared with the uniform temperature distribution model, the model considering the temperature gradients provided more accurate stress profiles in the solder interconnections and underfill fillet. The packages with prescribed delaminations resulted in significant changes in stress in the solder. From the parametric study, the coefficients of thermal expansion and the package configurations played significant roles in determining the stress level over the entire package, although they showed little influence on stresses profile within the individual components. These observations have been implemented to the multi-board layer chip scale packages (CSP), and its results are discussed.

• Applied Science and Convergence Technology
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• v.26 no.5
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• pp.133-138
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• 2017

We investigated the interface defect engineering and reaction mechanism of reduced transition layer and nitride layer in the active plasma process on 4H-SiC by the plasma reaction with the rapid processing time at the room temperature. Through the combination of experiment and theoretical studies, we clearly observed that advanced active plasma process on 4H-SiC of oxidation and nitridation have improved electrical properties by the stable bond structure and decrease of the interfacial defects. In the plasma oxidation system, we showed that plasma oxide on SiC has enhanced electrical characteristics than the thermally oxidation and suppressed generation of the interface trap density. The decrease of the defect states in transition layer and stress induced leakage current (SILC) clearly showed that plasma process enhances quality of $SiO_2$ by the reduction of transition layer due to the controlled interstitial C atoms. And in another processes, the Plasma Nitridation (PN) system, we investigated the modification in bond structure in the nitride SiC surface by the rapid PN process. We observed that converted N reacted through spontaneous incorporation the SiC sub-surface, resulting in N atoms converted to C-site by the low bond energy. In particular, electrical properties exhibited that the generated trap states was suppressed with the nitrided layer. The results of active plasma oxidation and nitridation system suggest plasma processes on SiC of rapid and low temperature process, compare with the traditional gas annealing process with high temperature and long process time.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.180-180
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• 2010

Thin film transistors (TFTs) based on oxide semiconductors have emerged as a promising technology, particularly for active-matrix TFT-based backplanes. Currently, an amorphous oxide semiconductor, such as InGaZnO, has been adopted as the channel layer due to its higher electron mobility. However, accurate and repeatable control of this complex material in mass production is not easy. Therefore, simpler polycrystalline materials, such as ZnO and $SnO_2$, remain possible candidates as the channel layer. Inparticular, ZnO-based TFTs have attracted considerable attention, because of their superior properties that include wide bandgap (3.37eV), transparency, and high field effect mobility when compared with conventional amorphous silicon and polycrystalline silicon TFTs. There are some technical challenges to overcome to achieve manufacturability of ZnO-based TFTs. One of the problems, the stability of ZnO-based TFTs, is as yet unsolved since ZnO-based TFTs usually contain defects in the ZnO channel layer and deep level defects in the channel/dielectric interface that cause problems in device operation. The quality of the interface between the channel and dielectric plays a crucial role in transistor performance, and several insulators have been reported that reduce the number of defects in the channel and the interfacial charge trap defects. Additionally, ZnO TFTs using a high quality interface fabricated by a two step atomic layer deposition (ALD) process showed improvement in device performance In this study, we report the fabrication of high performance ZnO TFTs with a $Si_3N_4$ gate insulator treated using plasma. The interface treatment using electron cyclotron resonance (ECR) $O_2$ plasma improves the interface quality by lowering the interface trap density. This process can be easily adapted for industrial applications because the device structure and fabrication process in this paper are compatible with those of a-Si TFTs.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.193.2-193.2
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• 2016

We evaluate the change in defects in the oxidized SiO2 grown on 4H-SiC (0001) by plasma assisted oxidation, by comparing with that of conventional thermal oxide. In order to investigate the changes in the electronic structure and electrical characteristics of the interfacial reaction between the thin SiO2 and SiC, x-ray photoelectron spectroscopy (XPS), X-ray absorption spectroscopy (XAS), DFT calculation and electrical measurements were carried out. We observed that the direct plasma oxide grown at the room temperature and rapid processing time (300 s) has enhanced electrical characteristics (frequency dispersion, hysteresis and interface trap density) than conventional thermal oxide and suppressed interfacial defect state. The decrease in defect state in conduction band edge and stress-induced leakage current (SILC) clearly indicate that plasma oxidation process improves SiO2 quality due to the reduced transition layer and energetically most stable interfacial state between SiO2/SiC controlled by the interstitial C.

• Korean Journal of Materials Research
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• v.26 no.12
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• pp.751-756
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• 2016

Graphite was diffusion-bonded by hot-pressing to W-25Re alloy using a Ti interlayer. For the joining, a uniaxial pressure of 25 MPa was applied at $1600^{\circ}C$ for 2 hrs in an argon atmosphere with a heating rate of $10^{\circ}C\;min^{-1}$. The interfacial microstructure and elemental distribution of the W-25Re/Ti/Graphite joints were analyzed by scanning electron microscopy (SEM). Hot-pressed joints appeared to form a stable interlayer without any micro-cracking, pores, or defects. To investigate the high-temperature stability of the W-25Re/Ti/Graphite joint, an oxy-acetylene torch test was conducted for 30 seconds with oxygen and acetylene at a 1.3:1 ratio. Cross-sectional analysis of the joint was performed to compare the thickness of the oxide layer and its chemical composition. The thickness of W-25Re changed from 250 to $20{\mu}m$. In the elemental analysis, a high fraction of rhenium was detected at the surface oxidation layer of W-25Re, while the W-25Re matrix was found to maintain the initial weight ratio. Tungsten was first reacted with oxygen at a torch temperature over $2500^{\circ}C$ to form a tungsten oxide layer on the surface of W-25Re. Then, the remaining rhenium was subsequently reacted with oxygen to form rhenium oxide. The interfacial microstructure of the Ti-containing interlayer was stable after the torch test at a temperature over $2500^{\circ}C$.

• Current Photovoltaic Research
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• v.9 no.4
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• pp.145-159
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• 2021

Light soaking (LS) stability in polymer solar cells (PSCs) has always been a challenge to achieve due to unstable photoactive layer-electrode interface. Especially, the electron transport layer (ETL) and photoactive layer interface limits the LS stability of PSCs. Herein, we have modified the most commonly used and robust zinc oxide (ZnO) ETL-interface using an organic dye molecule and a co-adsorbent. Power conversion efficiencies have been slightly improved but when these PSCs were subjected to long term LS stability chamber, equipped with heat and humidity (45℃ and 85% relative humidity), an outstanding stability in the case of ZnO/dye+co-adsorbent ETL containing devices have been achieved. The enhanced LS stability occurred due to the suppressed interfacial defects and robust contact between the ZnO and photoactive layer. Current density as well as fill factors have been retained after LS with the modified ETL as compared to un-modified ETL, owing to their higher charge collection efficiencies which originated from higher electron mobilities. Moreover, the existence of less traps (as observed from light intensity-open circuit voltage measurements and dark currents at -2V) are also found to be one of the reasons for enhanced LS stability in the current study. We conclude that the mitigation ETL-surface traps using an organic dye with a co-adsorbent is an effective and robust approach to enhance the LS stability in PSCs.

• Journal of Electrical Engineering and Technology
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• v.10 no.5
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• pp.2089-2098
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• 2015

With the continuous development in insulation of electrical equipment design, the reliability of the system has been enhanced. However, in the manufacturing process and during operation under continues stresses introduce local defects, such as voids between interfaces that can responsible to occurrence of partial discharge (PD), electric field distortion and accumulation of charges. These defects may lead to localize corrosion and material degradation of insulation system, and a serious threat to the equipment. A model of three layers of PI film with air gap is presented to understand the influence of interface and voids on exploitation conditions such as strong electrical field, PD activity and charge movement. The analytical analysis, and experimental results are good agreement and show that the lose contact between interfaces accumulate more residual charges and in consequences increase the electric field intensity and accelerates internal discharges. These residual charges are trapped charges, injected by the electrodes has often same polarity, so the electric field in cavities increases significantly and thus partial discharge inception voltage (PDIV) decreases. Contrary, number of PD discharge quantity increases due to interface. Interfacial polarization effect has opposite impact on electric field and PDIV as compare to void.

• Korean Journal of Materials Research
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• v.11 no.12
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• pp.1086-1090
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• 2001

Composition effects on microstructure and metallizing properties of the alumina sintered body were evaluated to develop the metallized alumina tubes having superior properties for electronic devices. SEM observation revealed that resultant micrographs and fractographs were varied with composition chance of additives and $SiO_2$-rich specimens showed better microstructural characteristics with uniform distribution of fine and round particles than other CaO-rich or MgO-rich ones. The resultant interfacial microstructure of the $SiO_2$-rich metallized alumina tubes also showed good metallizing properties with no defects between layers and uniform thickness of metallizing layer.

• Transactions on Electrical and Electronic Materials
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• v.17 no.6
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• pp.380-382
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• 2016

The mechanism for instability under PBS (positive bias stress) in amorphous SIZO (Si-In-Zn-O) thin-film transistors was investigated by analyzing the charge trapping mechanism. It was found that the bulk traps in the SIZO channel layer and the channel/dielectric interfacial traps are not created during the PBS duration. This result suggests that charge trapping in gate dielectric, and/or in oxide semiconductor bulk, and/or at the channel/dielectric interface is a more dominant mechanism than the creation of defects in the SIZO-TFTs.