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Thermo-Mechanical Interaction of Flip Chip Package Constituents  

박주혁 (세종대학교 기계공학과 생산기술연구소)
정재동 (세종대학교 기계공학과 생산기술연구소)
Publication Information
Journal of the Korean Society for Precision Engineering / v.20, no.10, 2003 , pp. 183-190 More about this Journal
Abstract
Major device failures such as die cracking, interfacial delamination and warpage in flip chip packages are due to excessive heat and thermal gradients- There have been significant researches toward understanding the thermal performance of electronic packages, but the majority of these studies do not take into account the combined effects of thermo-mechanical interactions of the different package constituents. This paper investigates the thermo-mechanical performance of flip chip package constituents based on the finite element method with thermo-mechanically coupled elements. Delaminations with different lengths between the silicon die and underfill resin interfaces were introduced to simulate the defects induced during the assembly processes. The temperature gradient fields and the corresponding stress distributions were analyzed and the results were compared with isothermal case. Parametric studies have been conducted with varying thermal conductivities of the package components, substrate board configurations. Compared with the uniform temperature distribution model, the model considering the temperature gradients provided more accurate stress profiles in the solder interconnections and underfill fillet. The packages with prescribed delaminations resulted in significant changes in stress in the solder. From the parametric study, the coefficients of thermal expansion and the package configurations played significant roles in determining the stress level over the entire package, although they showed little influence on stresses profile within the individual components. These observations have been implemented to the multi-board layer chip scale packages (CSP), and its results are discussed.
Keywords
Interfacial stress; Filp Chip; Thermo-mechanical performance; Finite Element Analysis; Delamination; Reliability;
Citations & Related Records
Times Cited By KSCI : 3  (Citation Analysis)
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1 Iliev, S. K., 'Thermal Performance Comparison of Chip-on-Board, Flip Chip-on-Board and Standard TQFP Package,' Proceeding of 14th IEEE SEMI-THERM Symposium, pp. 161-168, 1998   DOI
2 Zhou, T. and Hundt, M., 'Thermal Enhancement Guidelines for PQFP, BGA and Flip Chip,' Proceeding of NEPCON West, pp. 1139-1149, 1998
3 Sham, M. L., Xu, Z. Y. and Kim, J. K., 'Numerical Analysis of Delamination Failure and Interfacial Adhesion Measurements in Flip Chip Package,' International Conference of Electronic packaging, Tokyo, pp. 278-283, 2002
4 Lau, J. H. and Pao, Y. H., Solder Joint Reliability of BGA, CSP, Flip Chip and Fine Pitch SMT Assemblies, pp. 345-348, McGraw-Hill Inc, 1997
5 Zhou, T., Hundt, M., Villa, C., Bond, R. and Lao, T., 'Thermal Study for Flip Chip on FR-4 Boards,' Proc. of 47th Electronic Components and Technology Conference, pp. 879-884, 1997   DOI
6 Lau, J. H., Low Cost Flip Chip Technologies, pp. 235-238, McGraw-Hill lnc, 2000
7 Yao, Q. & Qu, J., 'Three-Dimensional versus Two-Dimensional Finite Element Modelling of Flip-Chip Packages,' Journal of Electronic Packaging, Vol. 121, pp. 196-201, 1999   DOI
8 Hwang, C. 8., 'Thermal Design for Flip Chip on Board in Natural Convection,' Proceedings of 15th IEEE SEMI-THERM Symposium, pp. 125-132, 1999   DOI
9 Han, S. J. and Huh, Y., 'Paddle Shift Analysis During Semiconductor Encapsulation,' J. of the KSPE, Vol. 18, No.5, pp. 147-155, 2001   과학기술학회마을
10 Han, S. J., Huh, Y. and Lee. S. C., 'A Study of Wire Sweep, Pre-conditioning and Paddle Shift during Encapsulation of Semiconductor Chips,' J. of the KSPE, Vol. 18, No.2, pp. 102-110, 2001   과학기술학회마을