• 한국표면공학회지
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• 제35권5호
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• pp.289-294
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• 2002

ZnTe films have been grown on (100) GaAs substrate with two representative problems. The one is lattice mismatch, the other is thermal expansion coefficients mismatch of ZnTe /GaAs. It claims here, the relationship of film thickness and defects distribution with (100) ZnTe/GaAs using hot wall epitaxy (HWE) growth was investigated by transmission electron microscopy (TEM). It analyzed on the two-sort side using TEM with cross-sectional transmission electron microscopy (XTEM) and high-resolution electron microscopy (HREM). Investigation into the nature and behavior of dislocations with dependence-thickness in (100) ZnTe/ (100) GaAs hetero-structures grown by transmission electron microscopy (TEM). This defects range from interface to 0.7 $\mu\textrm{m}$ was high density, due to the large lattice mismatch and thermal expansion coefficients. The defects of low density was range 0.7$\mu\textrm{m}$~1.8$\mu\textrm{m}$. In the thicker range than 1.8$\mu\textrm{m}$ was measured hardly defects.

• 공업화학
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• 제9권7호
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• pp.990-997
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• 1998

ECR 산소플라즈마를 이용하여 저온 확산법에 의해 서로 다른 종류의 기판에 마이크로파 출력, 기판의 위치 등을 실험변수로 실리콘 산화막을 제조하고, 열처리 전 후 물리 화학적 특성을 분석하여 Si/O 의 조성비, 산화막 표면의 morphology와 전기적 특성과의 관계를 살펴보았다. 마이크로파 출력이 높은 영역에서, 산화속도는 증가하지만 식각으로 인하여 표면조도가 증가하였다. 따라서 막내에 결함이 증가하고 기판자체에 걸리는 DC bias의 증가로 기상에 존재하는 산소 양이온이 다량 함유되어 산화막의 질이 저하되었다. 기판의 종류에 따라 기상에 존재하는 산소 양이온의 함량은 Si(100) $Si/SiO_2$계면에 존재하는 결함들은 줄일 수 있으나, 고정전하와 계면포획전하 밀도는 열처리와 무관하고 단지 기상에 존재하는 반응성 산소이온의 양과 기판자체 DS bias에 의존하였다. 마이크로파 출력이 300, 400 W인 실험조건에서 표면조도가 낮고, 계면결함밀도가 ${\sim}9{\times}10^{10}cm^{-2}eV^{-1}$로 $Si/SiO_2$계면에서 결함이 적은 양질의 산화막이 얻어졌다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.193.2-193.2
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• 2016

We evaluate the change in defects in the oxidized SiO2 grown on 4H-SiC (0001) by plasma assisted oxidation, by comparing with that of conventional thermal oxide. In order to investigate the changes in the electronic structure and electrical characteristics of the interfacial reaction between the thin SiO2 and SiC, x-ray photoelectron spectroscopy (XPS), X-ray absorption spectroscopy (XAS), DFT calculation and electrical measurements were carried out. We observed that the direct plasma oxide grown at the room temperature and rapid processing time (300 s) has enhanced electrical characteristics (frequency dispersion, hysteresis and interface trap density) than conventional thermal oxide and suppressed interfacial defect state. The decrease in defect state in conduction band edge and stress-induced leakage current (SILC) clearly indicate that plasma oxidation process improves SiO2 quality due to the reduced transition layer and energetically most stable interfacial state between SiO2/SiC controlled by the interstitial C.

• 한국전기전자재료학회논문지
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• 제17권6호
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• pp.580-585
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• 2004

Silicon dioxide (SiO$_2$) is widely used as a gate dielectric material for thin film transistors (TFT) and semiconductor devices. In this paper, SiO$_2$ films were grown by APCVD(Atmospheric Pressure chemical vapor deposition) at the high temperature. Experimental investigations were carried out as a function of $O_2$ gas flow ratios from 0 to 200 1pm. This article presents the SiO$_2$ gate dielectric studies in terms of deposition rate, refrative index, FT-IR, C-V for the gate dielectric layer of thin film transistor applications. We also study defect passivation technique for improvement interface or surface properties in thin films. Our passivation technique is Forming Gas Annealing treatment. FGA acts passivation of interface and surface impurity or defects in SiO$_2$ film. We used RTP system for FGA and gained results that reduced surface fixed charge and trap density of midgap value.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2018년도 춘계학술대회 논문집
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• pp.102-102
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• 2018

Electronic industry had required the finer size and the higher performance of the device. Therefore, 3-D die stacking technology such as TSV (through silicon via) and micro-bump had been used. Moreover, by the development of the 3-D die stacking technology, 3-D structure such as chip to chip (c2c) and chip to wafer (c2w) had become practicable. These technologies led to the appearance of HBM (high bandwidth memory). HBM was type of the memory, which is composed of several stacked layers of the memory chips. Each memory chips were connected by TSV and micro-bump. Thus, HBM had lower RC delay and higher performance of data processing than the conventional memory. Moreover, due to the development of the IT industry such as, AI (artificial intelligence), IOT (internet of things), and VR (virtual reality), the lower pitch size and the higher density were required to micro-electronics. Particularly, to obtain the fine pitch, some of the method such as copper pillar, nickel diffusion barrier, and tin-silver or tin-silver-copper based bump had been utillized. TCB (thermal compression bonding) and reflow process (thermal aging) were conventional method to bond between tin-silver or tin-silver-copper caps in the temperature range of 200 to 300 degrees. However, because of tin overflow which caused by higher operating temperature than melting point of Tin ($232^{\circ}C$), there would be the danger of bump bridge failure in fine-pitch bonding. Furthermore, regulating the phase of IMC (intermetallic compound) which was located between nickel diffusion barrier and bump, had a lot of problems. For example, an excess of kirkendall void which provides site of brittle fracture occurs at IMC layer after reflow process. The essential solution to reduce the difficulty of bump bonding process is copper to copper direct bonding below $300^{\circ}C$. In this study, in order to improve the problem of bump bonding process, copper to copper direct bonding was performed below $300^{\circ}C$. The driving force of bonding was the self-annealing properties of electrodeposited Cu with high defect density. The self-annealing property originated in high defect density and non-equilibrium grain boundaries at the triple junction. The electrodeposited Cu at high current density and low bath temperature was fabricated by electroplating on copper deposited silicon wafer. The copper-copper bonding experiments was conducted using thermal pressing machine. The condition of investigation such as thermal parameter and pressure parameter were varied to acquire proper bonded specimens. The bonded interface was characterized by SEM (scanning electron microscope) and OM (optical microscope). The density of grain boundary and defects were examined by TEM (transmission electron microscopy).

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제53권3호
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• pp.128-132
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• 2004

The perovskite ferroelectric materials of the PZT, SBT and BST series will attract much attention for application to ULSI devices. Among these materials, the BST ($Ba_0.6$$Sr_0.4$/$TiO_3$) is widely considered the most promising for use as an insulator in the capacitors of DRAMS beyond 1 Gbit and high density FRAMS. Especially, BST thin films have a good thermal-chemical stability, insulating effect and variety of Phases. However, BST thin films have problems of the aging effect and mismatch between the BST thin film and electrode. Also, due to the high defect density and surface roughness at grain boundarys and in the grains, which degrades the device performances. In order to overcome these weakness, we first applied the chemical mechanical polishing (CMP) process to the polishing of ferroelectric film in order to obtain a good planarity of electrode/ferroelectric film interface. BST ferroelectric film was fabricated by the sol-gel method. And then, we compared the surface characteristics before and after CMP process of BST films. We expect that our results will be useful promise of global planarization for FRAM application in the near future.

• 전기전자학회논문지
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• 제18권4호
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• pp.620-624
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• 2014

본 연구에서는, Ni/CNT/$SiO_2$ 구조의 4H-SiC MIS 캐패시터를 제작하고 전기적 특성을 조사하였다. 이를 통하여 4H-SiC MIS 소자에서 탄소나노튜브의 역할을 분석하고자 하였다. 탄소나노튜브는 이소프로필알코올과 혼합하여 $SiO_2$ 표면에 분산하였다. 소자의 전기적 특성 분석을 위하여 300-500K의 온도 범위에서 소자의 정전용량-전압 특성을 측정하였다. 밴드 평탄화 전압은 양의 방향으로 shift되었다. 정전용량-전압 그래프로부터 계면 포획 전하 밀도 및 산화막 포획 전하 밀도가 유도되었다. 산화막의 상태는 4H-SiC MIS 구조의 계면에서 전하 반송자 또는 결함 상태와 관련된다. 온도가 증가함에 따라 밴드 평탄화 전압은 음의 방향으로 shift되는 결과를 얻었다. 실험 결과로부터, Ni과 $SiO_2$ 계면에 탄소나노튜브를 첨가함에 따라 4H-SiC MIS 캐패시터의 게이트 특성을 조절 가능할 것으로 판단된다.

• 한국결정성장학회지
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• 제26권1호
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• pp.1-7
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• 2016

RE : YAG 단결정은 레이저 발진 소재로 다양한 성장 변수를 제어하면서 Czochralski법으로 성장된다. 성장과정 동안 고액계면의 온도구배 및 회전속도에 의해 발생하는 결함들은 결정의 광학적 특성 저하로 작용하기 때문에 결함 분석을 통한 결정 품질의 향상을 필요로 한다. 격자결함 밀도 분석(EPD)을 통하여 성장된 RE : YAG 단결정의 표면 결함 존재를 확인하였고, 이를 통해 투과전자현미경(TEM) 분석영역을 선택하였다. 선택한 영역의 시편은 트라이포드 연마 방법으로 제작하였고, 200 kV 투과전자현미경과 300 kV 전계 방사형 투과전자현미경(FE-TEM)을 사용하여 buckling, rod shaped, 내부응력에 의한 bend contours, 편석 등의 결함들을 관찰하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.199-199
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• 2011

Recently, Thin film transistors (TFTs) with amorphous oxide semiconductors (AOSs) can offer an important aspect for next generation displays with high mobility. Several oxide semiconductor such as ZnO, $SnO_2$ and InGaZnO have been extensively researched. Especially, as a well-known binary metal oxide, tin oxide ($SnO_2$), usually acts as n-type semiconductor with a wide band gap of 3.6eV. Over the past several decades intensive research activities have been conducted on $SnO_2$ in the bulk, thin film and nanostructure forms due to its interesting electrical properties making it a promising material for applications in solar cells, flat panel displays, and light emitting devices. But, its application to the active channel of TFTs have been limited due to the difficulties in controlling the electron density and n-type of operation with depletion mode. In this study, we fabricated staggered bottom-gate structure $SnO_2$-TFTs and patterned channel layer used a shadow mask. Then we compare to the performance intrinsic $SnO_2$-TFTs and doping hafnium $SnO_2$-TFTs. As a result, we suggest that can be control the defect formation of $SnO_2$-TFTs by doping hafnium. The hafnium element into the $SnO_2$ thin-films maybe acts to control the carrier concentration by suppressing carrier generation via oxygen vacancy formation. Furthermore, it can be also control the mobility. And bias stability of $SnO_2$-TFTs is improvement using doping hafnium. Enhancement of device stability was attributed to the reduced defect in channel layer or interface. In order to verify this effect, we employed to measure activation energy that can be explained by the thermal activation process of the subthreshold drain current.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.215.2-215.2
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• 2015

We fabricated dual active layer (DAL) thin film transistors (TFTs) with indium tin zinc oxide (ITZO) and indium gallium zinc oxide (IGZO) thin film layers using solution process. The ITZO and IGZO layer were used as the front and back channel, respectively. In order to investigate the bias stress stability of ITZO SAL (single active layer) and ITZO/IGZO DAL TFT, a gate bias stress of 10 V was applied for 1500 s under the dark condition. The SAL TFT composed of ITZO layer shows a poor positive bias stability of ${\delta}VTH$ of 13.7 V, whereas ${\delta}VTH$ of ITZO/IGZO DAL TFT was very small as 2.6 V. In order to find out the evidence of improved bias stress stability, we calculated the total trap density NT near the channel/gate insulator interface. The calculated NT of DAL and SAL TFT were $4.59{\times}10^{11}$ and $2.03{\times}10^{11}cm^{-2}$, respectively. The reason for improved bias stress stability is due to the reduction of defect sites such as pin-hole and pores in the active layer.