• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.05a
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• pp.82-85
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• 1992

In this study, charge pumping method was used to investigate the Si-SiO$_2$interface characteristics of the nonvolatile SNOSFET memory devices, fabricated using the CMOS 1 Mbit processes (1.2$\mu\textrm{m}$ design rule), with thin oxide layer of 30${\AA}$ thick and nitride layer of 525${\AA}$ thick on the n-type silicon substrate (p-channel). Charge pumping current characteristics with the pulse base level were measured for various frequencies, falling times and rising times. By means of the charge dynamics in a non-steady state, the average Si-SiO$_2$interface state density and capture cross section were determined to be 3.565${\times}$10$\^$11/cm$\^$-2/eV$\^$-1/ and 4.834${\times}$10$\^$-16/$\textrm{cm}^2$, respectively. However Si-SiO$_2$ interface state densities were disributed 2.8${\times}$10$\^$-11/～5.6${\times}$10$\^$11/cm$\^$-2/～6${\times}$10$\^$11/cm$\^$-2/eV$\^$-1/ in the lover half of energy gap.

• Proceedings of the IEEK Conference
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• summer
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• pp.343-347
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• 2004

High oxidation temperature of SiC shows a tendency of carbide formation at the interface which results in poor MOSFET transfer characteristics. Thus we developed oxidation processes in order to get low interface charge densities. N-type 6H-SiC MOS capacitors were fabricated by different oxidation processes: dry, wet, and dry­reoxidation. Gate oxidation and Ar anneal temperature was $1150^{\circ}C.$ Ar annealing was performed after gate oxidation for 30 minutes. Dry-reoxidation condition was $950^{\circ}C,$ H2O ambient for 2 hours. Gate oxide thickness of dry, wet and dry-reoxidation samples were 38.0 nm, 38.7 nm, 38.5 nm, respectively. Mo was adopted for gate electrode. To investigate quality of these gate oxide films, high frequency C- V measurement, gate oxide leakage current, and interface trapped charge densities (Dit) were measured. The interface trapped charge densities (Dit) measured by conductance method was about $4\times10^{10}[cm^{-1}eV^{-1}]$ for dry and wet oxidation, the lowest ever reported, and $1\times10^{11}[cm^{-1}eV^{-1}]$ for dry-reoxidation

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.34-39
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• 2014

This paper discusses the 3-level charge pumping (CP) method in planar-type Silicon-Oxide-High-k-Oxide-Silicon (SOHOS) and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) devices to find out the reason of the degradation of data retention properties. In the CP technique, pulses are applied to the gate of the MOSFET which alternately fill the traps with electrons and holes, thereby causing a recombination current Icp to flow in the substrate. The 3-level charge pumping method may be used to determine not only interface trap densities but also capture cross sections as a function of trap energy. By applying this method, SOHOS device found to have a higher interface trap density than SONOS device. Therefore, degradation of data retention characteristics is attributed to the many interface trap sites.

• Electrical & Electronic Materials
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• v.11 no.10
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• pp.24-31
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• 1998

Interfacial effect in polymetric composites have been studied extensively. This report deals mainly with the effects of interfacial space charge and interface structure. A model for the dynamic process of interfacial space charge accumulation is proposed. The new model might interpret some interface phenomena which is difficult to be explained in terms of traditional Maxwell-Wagner theory. An interface structure is also presented, by which the importance of surface treatment of glass Fiber for improving the properties of FRP could be well understood.

• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1407-1409
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• 1998

It was investigated that space charge characteristics and Breakdown characteristics of XLPE/EPDM laminates as a function of interfacial condition. When the chemical A was pasted in laminate interface, there was little space charge in XLPE/EPDM interface and it was shown that breakdown strength of XLPE/EPDM laminate was influenced by laminate condition.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.2313-2314
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• 2008

In this paper, the behaviour of charge carriers near the metal/polymer interface and its effects on conduction and breakdown phenomena are discussed. The metal/polymer interface strongly affects carrier injection, space charge formation and breakdown phenomena. Based on their experimental results, the physical backgrounds of the interfacial phenomena are explained.

• Transactions on Electrical and Electronic Materials
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• v.17 no.1
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• pp.25-28
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• 2016

We investigate the effect of interface states on the endurance of a charge trap flash (CTF) NOR array using charge pumping methods. The endurance test was completed from one cell selected randomly from 128 bit cells, where the memory window value after 10² program/erase (P/E) cycles decreased slightly from 2.2 V to 1.7 V. However, the memory window closure abruptly accelerated after 10³ P/E cycles or more (i.e. 0.97 V or 0.7 V) due to a degraded programming speed. On the other hand, the interface trap density (Nit) gradually increased from 3.13×10¹¹ cm⁻² for the initial state to 4×10¹² cm⁻² for 10² P/E cycles. Over 10³ P/E cycles, the Nit increased dramatically from 5.51×10¹² cm⁻² for 10³ P/E cycles to 5.79×10¹² cm⁻² for 10⁴ P/E cycles due to tunnel oxide damages. These results show good correlation between the interface traps and endurance degradation of CTF devices in actual flash cell arrays.

• Journal of Adhesion and Interface
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• v.22 no.4
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• pp.144-152
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• 2021

Understanding charge transfer across the interface between organic semiconductor and gate insulator gives insight into the development of high-performance organic memory as well as highly stable organic field-effect transistors (OFETs). In this work, we firstly unveil a novel interfacial charge transfer mechanism, in which hole transfer from organic semiconductor to polymer insulator was nonlinearly boosted by localized states coupling. For this, OFETs based on rubrene single crystal semiconductor and Mylar gate insulator were fabricated via vacuum lamination, which allows stable repetition of lamination and delamination between semiconductor and gate insulator. The surfaces of rubrene single crystal and Mylar film were selectively degraded by photo-induced oxygen diffusion and UV-ozone treatment, respectively. Consequently, we found that the interfacial charge transfer and resultant bias-stress effect were nonlinearly boosted by coupling between localized states in rubrene and Mylar. In particular, the small number of localized states in rubrene single crystal provided fluent pathway for interfacial charge transport.

• Journal of Adhesion and Interface
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• v.21 no.4
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• pp.129-134
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• 2020

Understanding charge trapping at the interface between conjugated semiconductor and polymer dielectric basically gives insight into the development of long-term stable organic field-effect transistors (OFET). Here, the charge transport properties of OFETs using polymer dielectric with various molecular weights (MWs) have been investigated. The conjugated semiconductor, pentacene exhibited morphology and crystallinity, insensitive to MWs of polymethyl methacrylate (PMMA) dielectric. Consequently, transfer curves and field-effect mobilities of as-prepared devices are independent of MWs. Under bias stress in humid environment, however, the drain current decay as well as transfer curve shift are found to increase as the MW of PMMA decreases (MW effect). The charge trapping induced by MW effect is irreversible, that is, the localized charges are difficult to be delocalized. The MW effect is caused by the variation in the density of polymer chain ends in the PMMA: the free volumes at the PMMA chain ends act as charge trap sites, corresponding to drain current decay depending on MWs of PMMA.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.453-456
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• 1999

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor)NVSM(nonvolatile semiconductor memory) cell were investigated by single charge pumping method. The used device was fabricated by 0.35 7m standard logic fabrication including the ONO cell process. This ONO dielectric thickness is tunnel oxide 24 $\AA$, nitride 74 $\AA$, blocking oxide 25 $\AA$, respectively. Keeping the pulse base level in accumulation and pulsing the surface into inversion with increasing amplitudes, the charge pumping current flow from the single junction. Using the obtained I$_{cp}$-V$_{h}$ curve, the local V$_{t}$ distribution, doping concentration, lateral interface trap distribution and lateral memory trap distribution were extracted. The maximum N$_{it}$($\chi$) of 1.62$\times$10$^{19}$ /cm$^2$were determined.mined.d.