• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.239-242
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• 1998

Ca $F_2$ films have superior gate insulator properties than conventional gate insulator such as $SiO_2$, Si $N_{x}$, $SiO_{x}$, and T $a_2$ $O_{5}$ to the side of lattice mismatch between Si substrate and interface trap charge density( $D_{it}$). Therefore, this material is enable to apply Thin Film Transistor(TFT) gate insulator. Most of gate oxide film have exhibited problems on high trap charge density, interface state in corporation with O-H bond created by mobile hydrogen and oxygen atom. This paper performed Ca $F_2$ property evaluation as MIM, MIS device fabrication. Ca $F_2$ films were deposited at the various substrate temperature using a thermal evaporation. Ca $F_2$ films was grown as polycrystalline film and showed grain size variation as a function of substrate temperature and RTA post-annealing treatment. C-V, I-V results exhibit almost low $D_{it}$(1.8$\times$10$^{11}$ $cm^{-1}$ /le $V^{-1}$ ) and higher $E_{br}$ (>0.87MV/cm) than reported that formerly. Structural analysis indicate that low $D_{it}$ and high $E_{br}$ were caused by low lattice mismatch(6%) and crystal growth direction. Ca $F_2$ as a gate insulator of TFT are presented in this paper paperaper

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.2
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• pp.101-106
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• 2009

In this paper, Thin films of $HfO_2$/Hf were deposited on p-type wafer by Atomic Layer Deposition (ALD). We studied the electrical and material characteristics of $HfO_2$/Hf/Si MOS capacitor depending on thickness of Hf metal layer. $HfO_2$ films were deposited using TEMAH and $O_3$ at $350^{\circ}C$. Samples were then annealed using furnace heating to $500^{\circ}C$. Round-type MOS capacitors have been fabricated on Si substrates with $2000\;{\AA}$-thick Pt top electrodes. The composition rate of the dielectric material was analyzed using TEM (Transmission Electron Microscopy), XRD (X-ray Diffraction) and XPS (X-ray Photoelectron Spectroscopy). Also the capacitance-voltage (C-V), conductance-voltage (G-V), and current-voltage (I-V) characteristics were measured. We calculated the density of oxide trap charges and interface trap charges in our MOS device. At the interface between $HfO_2$ and Si, both Hf-Si and Hf-Si-O bonds were observed, instead of Si-O bond. The sandwiched Hf metal layer suppressed the growing of $SiO_x$ layer so that $HfSi_xO_y$ layer was achieved. And finally, the generation of both oxide trap charge and interface trap charge in $HfO_2$ film was reduced effectively by using Hf metal layer.

• Journal of Electrical Engineering and Technology
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• v.10 no.2
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• pp.647-652
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• 2015

A fully coupled finite element analysis (FEA) technique was developed for analyzing the discharge phenomena and dielectric liquid flow while considering surface charge density effects in dielectric flow guidance. In addition, the simulated speed of surface charge propagation was compared and verified with the experimental results shown in the literature. Recently, electrohydrodynamics (EHD) techniques have been widely applied to enhance the cooling performance of electromagnetic systems by utilizing gaseous or liquid media. The main advantage of EHD techniques is the non-contact and low-noise nature of smart control using an electric field. In some cases, flow can be achieved using only a main electric field source. The driving sources in EHD flow are ionization in the breakdown region and ionic dissociation in the sub-breakdown region. Dielectric guidance can be used to enhance the speed of discharge propagation and fluidic flow along the direction of the electric field. To analyze this EHD phenomenon, in this study, the fully coupled FEA was composed of Poisson's equation for an electric field, charge continuity equations in the form of the Nernst-Planck equation for ions, and the Navier-Stokes equation for an incompressible fluidic flow. To develop a generalized numerical technique for various EHD phenomena that considers fluidic flow effects including dielectric flow guidance, we examined the surface charge accumulation on a dielectric surface and ionization, dissociation, and recombination effects.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.2
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• pp.319-324
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• 2012

This paper introduces a 2-dimensional touch screen panel driver based on an improved capacitive sensing circuit. The improved capacitive sensing circuit based on charge pump can eliminate the remaining charges of the intermediate nodes, which may cause output voltage drift. The touch screen panel driver with mixed-mode circuits was built and simulated using Cadence Spectre. Verilog-A models the digital circuits effectively and enables them to interface with analog circuits easily. From the simulation results, we can verify the reliable operations of the simple structured touch screen panel driver based on the improved capacitive sensing circuit offering no voltage drift.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.3
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• pp.529-536
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• 2019

In order to apply a piezoelectric energy harvester to a smart sensor system, an energy harvest interface circuit including an AC-DC rectifier is required. In this paper, we compared the performance of full bridge rectifier, which is a typical energy harvester interface circuit, and synchronous piezoelectric energy harvest interface circuit by using board-level simulation. As a result, the output power of a synchronous electric charge extraction(: SECE) circuit is about four times larger than that of the full bridge rectifier, and there is little load variation. And a high voltage comparator, which is essential for the SECE circuit for the piezoelectric energy harvester with an output voltage of 40V or more, was designed using 0.35 um BCD process. The SECE circuit using the designed high-voltage comparator proved that the output power is 427 % higher than the FBR circuit.

• Journal of Photoscience
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• v.1 no.1
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• pp.53-59
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• 1994

Molecular orientation and polarity of solubilization site of dipolar azobenzenes solubilized in micellar solutions are discussed. The polarity of solubilization was estimated by using Taft $\pi$$^*$ scale with linear solvation energy relationship, $\Delta$E=$\Delta$E$_0$ + S($\pi$$^*$ + d$\delta$)+a$\alpha$ + b$\beta$. Hydrogen bonding effects were taken into account for the estimation of micropolarity. The polarity that azobenzenes experienced in the miceliar solutions was close to water which represented that the azobenzenes were mostly solubilized at the interface. For the orientations of azobenzenes were concerned, the nitro group of NPNOH faced the interface and the hydroxy group of NPNO$^-$ located at the interfacial area.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.10
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• pp.1528-1534
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• 1989

Photoeffects at the p-GaP semiconductor/CsNO3 electrolyte interface were investigated in terms of their current-voltage characteristics. The photoeffects at the semiconductor-electrolyte interfaces and their photocurrent variations are verified using Ar ion laser and continuous cyclic voltammetric methods. The mechanism of charge transfer at the photogeneration in the depletion layer rather than the photodecomposition of the p-GaP semiconductor electrode surface and/or the water photoelectrolysis. The adsorption of Cs+ ions at the interface is physical adsorption.

• 전기의세계
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• v.29 no.2
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• pp.111-117
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• 1980

Contacts formed by vacuum evaporation of As-Te-Si-Ge chalcogenide glass onto Al metal (99.9999%) are studied by measuring paralle capacitance C(V), Cp(w), resistance R(V), Rp(w), and I-V characteristics. The fact that contact metal alloying produced high-resistance region is confirmed from the measurements of parallel capacitance and resistance. From the I-V characteristics in the pre-switcing region, it is found that electronic conduction and sitching occurs in the vicinity of metal-amorphous semiconductor interface. From the experimental obsevations, it is concuded that the current flow in the thin film is space-charge limited current (SCLC) due to the tunneling of electrons through the energy barriers.

• Journal of Adhesion and Interface
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• v.21 no.3
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• pp.86-92
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• 2020

We confirmed the effects on the device performances and the charge injection characteristics of organic field-effect transistor (OFET) by selectively differently controlling the surface energies on the contact region of the substrate where the source/drain electrodes are located and the channel region between the two electrodes. When the surface energies of the channel and contact regions were kept low and increased, respectively, the field-effect mobility of the OFET devices was 0.063 ㎠/V·s, the contact resistance was 132.2 kΩ·cm, and the subthreshold swing was 0.6 V/dec. They are the results of twice and 30 times improvements compared to the pristine FET device, respectively. As the results of analyzing the interfacial trap density according to the channel length, a major reason of the improved device performances could be anticipated that the pi-pi overlapping direction of polymer semiconductor molecules and the charge injection pathway from electrode is coincided by selective surface treatment in the contact region, which finally induces the decreases of the charge trap density in the polymer semiconducting film. The selective surface treatment method for the contact region between the electrode and the polymer semiconductor used in this study has the potential to maximize the electrical performances of organic electronics by being utilized with various existing processes to lower the interface resistance.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.4
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• pp.92-100
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• 1985

New N+N/P HLE solar cells with N+ surface charge accumulated layer in the emitter region are fabricated on the N/P Si epiwafer by incorporating high fixed positive charge density (Qss) at the Si-AR layer interface. Solar cells are classified into two categories, i.e, OCI and NCI Cell depending on AR layer, SiOl and Si3 N4/sioxynitride layer respectively. The distribution of Qss in the Si-AR layer interface is examined by C-V plot. It shows that the surface charge accumulated layer is formed more effectively in the NCI cell (Qss=1.79-1.84$\times$1012cm-2) than in the OCI cell (Qss=3.03~4.40$\times$1011 cm-2). The efficiency characteristics are evaluated under the JCR halogen lamp of 100 mw/cm2. The average (maximum) conversion efficiency for active area is 15.18 (15.46)% in the OCI cell and 16.31 (17.07)% in the NCI cell.