• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.131-139
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• 2013

To overcome the limitations in performance and power consumption of traditional electrical interconnection based network-on-chips (NoCs), a hybrid optical network-on-chip (HONoC) architecture using optical interconnects is emerging. However, the HONoC architecture should use circuit-switching scheme owing to the overhead by optical devices, which worsens the latency unfairness problem caused by frequent path collisions. This resultingly exert a bad influence in overall performance of the system. In this paper, we propose a new task mapping algorithm for optimizing latency by reducing path collisions. The proposed algorithm allocates a task to a certain processing element (PE) for the purpose of minimizing path collisions and worst case latencies. Compared to the random mapping technique and the bandwidth-constrained mapping technique, simulation results show the reduction in latency by 43% and 61% in average for each $4{\times}4$ and $8{\times}8$ mesh topology, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.83-93
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• 2014

It is a widespread concern that electrical interconnection based network-on-chip (NoC) will ultimately face the limitation in communication bandwidth, transmission latency and power consumption in the near future. With the development of silicon photonics technology, a hybrid optical network-on-chip (HONoC) which embraces both electrical- and optical interconnect, is emerging as a promising solution to overcome these problems. Today's leading edge systems-on-chips (SoCs) comprise heterogeneous many-cores for higher energy efficiency, therefore, extended study beyond regular topology based NoC is required. This paper proposes an energy and latency optimization topology design technique for HONoC taking into account the traffic characteristics of target applications. The proposed technique is implemented with genetic algorithm and simulation results show the reduction by 13.84% in power loss and 28.14% in average latency, respectively.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.2
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• pp.211-218
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• 2015

This paper describes the implementation of the accelerated virtual switch using Intel DPDK(Data Plane Development Kit), and evaluates the virtual network functions of the virtual switch which is one of the most important components to build a virtual network for cloud computing. Nowadays, new information service platforms are appeared from the interconnection of intelligent IT systems like IoT(Internet of Things). And many companies want to use the new service platform for their new application service. The companies can apply there new service early which needs small investment and responses adaptively to the fast change of consumer environment. Using cloud computing technology, the new business service can be introduced as a commercial IT service for the time to market. In this study, an implementation and investigation were performed for the accelerated virtual switch, called Intel DPDK virtual switch, which is using multi processors in network interface card for virtual network functions. It can be useful for Internet-oriented companies to leverage the new cloud service and businesses for its creativeness.

• Journal of the Korea Society for Simulation
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• v.25 no.4
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• pp.43-52
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• 2016

Wireless sensor network (WSN) technology has been implemented using commercial off-the-shelf microcontrollers (MCUs), In this paper, we propose a simulation environment to realize the physical evaluation of FPGA-based node by considering vertically cross-layered WSN in terms of physical node device and network interconnection perspective. The proposed simulation framework emulates the physical FPGA-based sensor nodes to interoperate with the NS3 through the runtime infrastructure (RTI). For the emulation and interoperation of FPGA-based nodes, we extend a vendor-providing FPGA design tool from the host computer and a script to execute the interoperation procedures. The standalone NS-3 is also revised to perform interoperation through the RTI. To resolve the different time-advance mechanisms between the FPGA emulation and event-driven NS3 simulation, the pre-simulation technique is applied to the proposed environment. The proposed environment is applied to IEEE 802.15.4-based low-rate, wireless personal area network communication.

• Journal of KIISE:Information Networking
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• v.29 no.6
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• pp.696-705
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• 2002

This paper presents a new copy network for multicast ATM switches. Many studies have been carried out up to date since the proposition of Lee's copy network. However, the overflows and cell conflicts within the switch have still been raised a problem in argument. In order to reduce those problems, we proposed a 3-dimensional multicast switching architecture which has shared buffers in this paper. The proposed architecture can reduce the overflows and cell conflicts through multiple paths and output ports even in the high load environments. Also, we proposed a cell splitting algorithm which handles the cell in the case of large fan-out, and a copy network to increase throughput by expanding the Lee's Broadcast Banyan Network(BBN). Cell copy uses the Boolean interval splitting algorithm and the multicast pattern of the cells according to the self-routing characteristics of the network. In the proposed copy network, we improve the problems such as overflow, cell splitting of large fanout, cell conflicts, etc., which were still existed in the Lee's network. The results of performance evaluation by computer simulation show that the proposed scheme has better throughput, cell loss rate and cell delay than the conventional method.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.2
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• pp.177-187
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• 2000

In the past several years, many systems which adopted ring topology with high-speed unidirectional point-to-point links have emerged to overcome the limit of bus for interconnection network of clustered multiprocessor system. However, rapid increase of processor speed and performance improvement of local bus and memory system limit scalability of system with point-to-point link of standard bandwidth. Therefore, necessity to extend bandwidth is emphasized. In this paper, we adopt PANDA system as base model, which is clustering-based multiprocessor system. By simulating a model adopting commercial processor and local bus specification, we show that point-to-point link is bottleneck of system performance, and bandwidth expansion by more than 200% is needed. To expand bandwidth of interconnection network, it needs excessive design cost and time to develop new point-to-point link with doubled bandwidth. As an alternative to double bandwidth, we propose several ways to implement dual ring -simple dual ring, transaction-separated dual ring, direction-separated dual ring- by using off-the-shelf point-to-point links with IEEE standard bandwidth. We analyze pros. and cons. of each model compared with doubled-bandwidth single ring by simulation.

• The KIPS Transactions:PartA
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• v.12A no.6 s.96
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• pp.557-562
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• 2005

Throughput and latency of interconnection network are important factors of the performance of multiprocessor systems. The dual-link CC-NUMA architecture using point-to-point unidirectional link is one of the popular structures in high-end commercial systems. In terms of optimal path between nodes, several paths exist with the optimal hop count by its native multi-path structure. Furthermore, transaction latency between nodes is affected by congestion of links on the transaction path. Hence the transaction latency may get worse if the transactions make a hot spot on some links. In this paper, I propose a dynamic transaction routing algorithm that maintains the balanced link utilization with the optimal path length, and I compare the performance with the fixed path method on the dual-link CC-NUMA systems. By the proposed method, the link competition is alleviated by the real-time path selection, and consequently, dynamic transaction algorithm shows a better performance. The program-driven simulation results show $1{\~}10\%$ improved fluctuation of link utilization, $1{\~}3\%$ enhanced acquirement of link, and $1{\~}6\%$ improved system performance.

• Journal of Internet Computing and Services
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• v.8 no.5
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• pp.133-140
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• 2007

Currently, as the requirement for high quality Internet access from anywhere at anytime is consistently increasing, the interconnection of pure ad hoc networks to fixed IP networks becomes increasingly important. Such integrated network, referred to as hybrid ad hoc networks, can be extended to many applications, including Sensor Networks, Home Networks, Telematics, and so on. We focus on some data communication problems of hybrid ad hoc networks, such as broadcasting and routing. In particular. power failure of mobile terminals is the most important factor since it affects the overall network lifetime. We propose an energy-efficient routing protocol based on clustering for hybrid ad hoc networks. By applying the index-based data broadcasting and selective tuning methods, the infra system performs the major operations related to clustering and routing on behalf of ad hoc nodes. The proposed scheme reduces power consumption as well as the cost of path discovery and maintenance, and the delay required to configure the route.

• Journal of Korea Multimedia Society
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• v.6 no.3
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• pp.556-564
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• 2003

A Star and Pancake graph also have such a good property of a hypercube and have a low network cost than the hypercube. A Macro-star graph which has the star graph as a basic module has the node symmetry, the maximum fault tolerance, and the hierarchical decomposition property. And, it is an interconnection network which improves the network cost against the Star graph. In this paper, we propose a method to embed between Star graph, Pancake graph, and Macro-star graph using the edge definition of graphs. We prove that the Star graph $S_n$ can be embedded into Pancake graph $P_n$ with dilation 4, and Macro-star graph MS(2,n) can be embedded into Pancake graph $P_{2n＋1}$ with dilation 4. Also, we have a result that the embedding cost, a Pancake graph can be embedded into Star and Macro-star graph, is O(n).

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.5_6
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• pp.280-289
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• 2003

Deadlock recovery-based routing algorithms in wormhole networks have gained attraction due to low hardware complexity and high routing adaptability Progressive deadlock recovery techniques require a few dedicated resources to transmit deadlocked packets rather than killing them. Selection of deadlocked packets is primarily based on time-out value which should be carefully determined considering various traffic patterns or packet length. By its nature, current techniques using time-out accompany unignorable number of false deadlock detections especially in a heavy-loaded network or with long packet size. Moreover, when a deadlock occurs, more than one packet may be marked as deadlocked, which saturate the resources allocated for recovery. This paper proposes more accurate deadlock detection scheme which does not make use of time-out to declare deadlock. The proposed scheme reduces the probability to detect false deadlocks considerably. Furthermore, a single message is selected as deadlocked for each cycle of blocked messages, thereby eliminating recovery overheads.