• Journal of Advanced Navigation Technology
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• v.15 no.4
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• pp.640-645
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• 2011

The educational exchange through e-learning is working very well in such case as develop e-learning, development of various learning tools, cooperative practical use of e-learning contents, etc. However because there were no considerations of LMS(Learning Management System) interconnection when each systems were developed, the exchange through e-learning is starting to raise a problem. Hence in this thesis, this paper presents designed model about efficient LMS interconnection through analysis case of exchange through e-learning and deduce problem. In the first place essential part for is defied study such as lecture establishment data, lecture data, user data, class data, student learning tracking to interconnection data, then constituted data interconnection table used view by data interconnection process. By experiment result, the accessibility between students and professors was more convenience, and decreased work process by less data exchange. Henceforth there are researches in development of various essential parts for study, considered security of LMS interconnection.

• Korean Chemical Engineering Research
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• v.52 no.1
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• pp.26-39
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• 2014

Cu interconnection in electronic devices is fabricated via damascene process including Cu electrodeposition. In this review, Cu electrodeposition and superfilling for fabricating Cu interconnection are introduced. Superfilling results from the influences of organic additives in the electrolyte for Cu electrodeposition, and this is enabled by the local enhancement of Cu electrodeposition at the bottom of filling feature formed on the wafer through manipulating the surface coverage of organic additives. The dimension of metal interconnection has been constantly reduced to increase the integrity of electronic devices, and the width of interconnection reaches the range of few tens of nanometer. This size reduction raises the issues, which are the deterioration of electrical property and the reliability of Cu interconnection, and the difficulty of Cu superfilling. The various researches on the development of organic additives for the modification of Cu microstructure, the application of pulse and pulse-reverse electrodeposition, Cu-based alloy superfilling for improvement of reliability, and the enhancement of superfilling phenomenon to overcome the current problems are addressed in this review.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.30 no.4 s.247
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• pp.373-378
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• 2006

We present the design, fabrication, and characterization of a multi-chip microelectrofluidic bench, achieving both electrical and fluidic interconnections with a simple, low-loss and low-temperature electrofluidic interconnection method. We design 4-chip microelectrofluidic bench, having three electrical pads and two fluidic I/O ports. Each device chip, having three electrical interconnections and a pair of two fluidic I/O interconnections, can be assembled to the microelectofluidic bench with electrical and fluidic interconnections. In the fluidic and electrical characterization, we measure the average pressure drop of $13.6{\sim}125.4$ Pa/mm with the nonlinearity of 3.1 % for the flow-rates of $10{\sim}100{\mu}l/min$ in the fluidic line. The pressure drop per fluidic interconnection is measured as 0.19kPa. Experimentally, there are no significant differences in pressure drops between straight channels and elbow channels. The measured average electrical resistance is $0.26{\Omega}/mm$ in the electrical line. The electrical resistance per each electrical interconnection is measured as $0.64{\Omega}$. Mechanically, the maximum pressure, where the microelectrofluidic bench endures, reaches up to $115{\pm}11kPa$.

• ETRI Journal
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• v.35 no.6
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• pp.1152-1155
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• 2013

A cost-effective and simple solder on pad (SoP) process is proposed for a fine-pitch microbump interconnection. A novel solder bump maker (SBM) material is applied to form a 60-${\mu}m$ pitch SoP. SBM, which is composed of ternary Sn3.0Ag0.5Cu (SAC305) solder powder and a polymer resin, is a paste material used to perform a fine-pitch SoP through a screen printing method. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder, the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. Test vehicles with a daisy chain pattern are fabricated to develop the fine-pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si chip has 6,724 bumps with a 45-${\mu}m$ diameter and 60-${\mu}m$ pitch. The chip is flip chip bonded with a Si substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of the underfill. The optimized bonding process is validated through an electrical characterization of the daisy chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and microbump interconnection using a screen printing process.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.13-18
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• 2012

By the need for high-speed data transmission in PCB, the studies on the optical PCB has been conducted with optical interconnection and its packaging technology. Particularly, the polymer-based optical interconnection has been extensively studied with the advantages such as cost-effective and ease of process. For high-efficiency and passive alignment, the studies were performed using the 45 degree mirrors, MT connector, and etc. In this work, integrated PLC device and fiber alignment array block was fabricated by using imprint technology to solve the alignment and array problem of optical device and the optical fiber. The fabricated integrated block for optical interconnection of PLC device has achieved higher precision of decreasing the dimensional error of the patterns by optimization of process and its insertion loss has an average value of 4.03dB, lower than criteria specified by international standard. In addition, a optical waveguide with built-in lens has been proposed for high-efficiency and passive alignment. By simulation, it was confirmed that the proposed structure has higher coupling efficiency than conventional no-lens structure and has the broad tolerance for the spatial offset of optical waveguide.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.5B
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• pp.324-329
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• 2005

In the traditional telephone services, the settlement method for usage of facilities has been systematically and reasonably arranged based on the cost. Through the advanced technology, the telecommunication services such as the convergence of voice-data, wire-wireless, communication-broadcasting, etc are offering. So, new settlement method in the broadband convergence network (BCN) should be necessary. This paper suggests inter-companies settlement method in the broadband network using interconnection bandwidth and transmission distance factor. By reflecting the facility cost weight on each BCN level, the cost settlement for various services can be easily done. As the settlement model for BCN, the inter-companies interconnection and settlement can be normalized by interconnection bandwidth and transmission distance factors.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.5
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• pp.60-70
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• 1995

As a Basic study to implement a wide-band photonic switching sysetm, we proposed a scheme of free-space-division-multiplexed photonic switching based on a holographic interconnectio method and carried out simple experiments on it. First, we recorded holgraphic interconnection element array for nonblocking optical interconnections. Just a single stage of the array realizes full optical interconnections between NN${\times}$NN input prots and NN${\times}$NN output ports in 3-D space. Next, in reading of the array for optical internnections, we showed that the zeroth-order diffacted beam could be eliminated in the output port by introducing a right angle prism. The elimination of the zeroth-order diffracted beam reduces optical noise in the output ports and provides conveniences of interconnection control in our scheme. Finally, from the experiments on ON-OFF switching of the optical interconnection paths one by one using a spatial (display of the liquid crystal telecision), we showed the feasibility of photonic wsitching based on the holographic interconnection method. We also estimated approximately the maximum interconnectio scale that can be realized without difficulty with current optical devices.

• ETRI Journal
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• v.41 no.5
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• pp.670-683
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• 2019

In this paper, we analyzed the signal integrity of a system interconnection module for a proposed high-density server. The proposed server integrates several components into a chassis. Therefore, the proposed server can access multiple computing resources. To support the system interconnection, among the highly integrated computing resources, the interconnection module, which is based on Serial RapidIO, has been newly adopted and supports a bandwidth of 800 Gbps while routing 160 differential signal traces. The module was designed for two different stack-up types on a printed circuit board. Each module was designed into 12- (version 1) and 14-layer (version 2) versions with thicknesses of 1.5T and 1.8T, respectively. Version 1 has a structure with two consecutive high-speed signal-layers in the middle of two power planes, whereas Version 2 has a single high-speed signal placed only in the space between two power planes. To analyze the signal integrity of the module, we probed the S-parameters, eye-diagrams, and crosstalk voltages. The results show that the high-speed signal integrity of Version 2 has a better quality than Version 1, even if the signal trace length is increased.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.289-440
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• 1998

This paper describes an interconnection network structure which transports information among processors through a high speed ATM switch. To efficiently use the high speed ATM switch for the message-based multiprocessor, we implemented the cell router that performs multiplexing and demultiplexing of cells from/to processors. In this system, we use the expanded internal cell format including 3bytes for switch routing information. This interconnection network has 3 stage routing strategies: ATM switch routing using switch routing information, cell router routing using a virtual path identifier (VPI) and cell reassembly routing using a virtual channel indentifier (VCI). The interconnection network consists of the NxN folded switch and N cell routers with the M processor interface. Therefore, the maximum number of NxM processors can be interconnected for message communication. This interconnection network using the ATM switch makes a significant improvement in terms of message passing latency and scalability. Additionally, we evaluated the transmission overhead in this interconnection network using ATM switch.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.7 no.5
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• pp.395-407
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• 1996

In this paper, we describe the crossover of the parasitic capacitance at the interconnections for the system miniature, analyse ground capacitance and mutual capacitance due to actually coupled line in the ICs or MCMs. From the results of deviding interconnection line with infinite parts, using Green's function with image charge method and moments, we could obtain 70% decrease of system runtime parasitic inductance because of simplicity of transforming formular.