• Journal of Power Electronics
• /
• v.9 no.4
• /
• pp.544-552
• /
• 2009

This paper presents a novel spring pressure contact interconnect technique for medium power integrated power electronics modules (IPEMs). The key technology of this interconnection is a spring which is made from Be-Cu alloy. By means of the string pressure contact, sufficient press-contact force and good electrical interconnection can be achieved. Another important advantage is that the spring exhibits excellent performance in enduring thermo-mechanical stress. In terms of manufacture procedure, it is also comparatively simple. A 4 kW half-bridge power inverter module is fabricated to demonstrate the performance of the proposed pressure contact technique. Electrical, thermal and mechanical test results of the packaged device are reported. The results of both the simulation and experiment have proven that a good performance can be achieved by the proposed pressure contact technique for the medium power IPEMs.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
• /
• v.24 no.2
• /
• pp.51-57
• /
• 2013

The current expanding mobile markets incessantly demands small form factor, low power consumption and high aggregate throughput for silicon-level integration such as memory to logic system. One of emerging solution for meeting this high market demand is 3D through silicon stacking (TSS) technology. Main challenges to bring 3D TSS technology to the volume production level are establishing a cost effective supply chain and building a reliable manufacturing processes. In addition, this technology inherently help increase number of IOs and shorten interconnect length. With those benefits, however, potential signal and power integrity risks are also elevated; increase in PDN inductance, channel loss on substrate, crosstalk and parasitic capacitance. This paper will report recent progress of wide IO memory to high count TSV logic device assembly development work. 28 nm node TSV test vehicles were fabricated by the foundry and assembled. Successful integration of memory wide IO chip with less than a millimeter package thickness form factor was achieved. For this successful integration, we discussed potential signal and power integrity challenges. This report demonstrated functional wide IO memory to 28 nm logic device assembly using 3D package architecture with such a thin form factor.

• Korean Journal of Materials Research
• /
• v.20 no.6
• /
• pp.319-325
• /
• 2010

3-D IC integration enables the smallest form factor and highest performance due to the shortest and most plentiful interconnects between chips. Direct metal bonding has several advantages over the solder-based bonding, including lower electrical resistivity, better electromigration resistance and more reduced interconnect RC delay, while high process temperature is one of the major bottlenecks of metal direct bonding because it can negatively influence device reliability and manufacturing yield. We performed quantitative analyses of the interfacial properties of Al-Al bonds with varying process parameters, bonding temperature, bonding time, and bonding environment. A 4-point bending method was used to measure the interfacial adhesion energy. The quantitative interfacial adhesion energy measured by a 4-point bending test shows 1.33, 2.25, and $6.44\;J/m^2$ for 400, 450, and $500^{\circ}C$, respectively, in a $N_2$ atmosphere. Increasing the bonding time from 1 to 4 hrs enhanced the interfacial fracture toughness while the effects of forming gas were negligible, which were correlated to the bonding interface analysis results. XPS depth analysis results on the delaminated interfaces showed that the relative area fraction of aluminum oxide to the pure aluminum phase near the bonding surfaces match well the variations of interfacial adhesion energies with bonding process conditions.

• Journal of the Microelectronics and Packaging Society
• /
• v.11 no.3 s.32
• /
• pp.9-15
• /
• 2004

We investigated the electrical properties of copolymer low-k materials that are compromised of the PMSSQ(Poly Methyl Silsesquioxane)-based matrix with the BTMSE (Bis Tri Methoxy Silyl Ethane) additives. We manufactured MIS-type test samples using the copolymer as the insulator and measured their leakage current and failure time by means of the BTS (bias-temperature-stress) test. The failure time was observed to decrease drastically when the porosity of the copolymer was increased over $30\%$. From the measurement of failure time with respect to temperature. the activation energy of Cu drift through the copolymer was calculated to be 1.51 eV.

• Corrosion Science and Technology
• /
• v.6 no.6
• /
• pp.282-285
• /
• 2007

Smaller size and higher integration of electronic systems make narrower interconnect pitch not only in chip-level but also in package-level. Moreover electronic systems are required to operate in harsher conditions, that is, higher current / voltage, elevated temperature / humidity, and complex chemical contaminants. Under these severe circumstances, electronic components respond to applied voltages by electrochemically ionization of metals and conducting filament forms between anode and cathode across a nonmetallic medium. This phenomenon is called as the electrochemical migration. Many kinds of metal (Cu, Ag, SnPb, Sn etc) using in electronic packages are failed by ECM. Eutectic SnPb which is used in various electronic packaging structures, that is, printed circuit boards, plastic-encapsulated packages, organic display panels, and tape chip carriers, chip-on-films etc. And the material for soldering (eutectic SnPb) using in electronic package easily makes insulation failure by ECM. In real PCB system, not only metals but also many chemical species are included. And these chemical species act as resources of contamination. Model test systems were developed to characterize the migration phenomena without contamination effect. The serpentine-shape pattern was developed for analyzing relationship of applied voltage bias and failure lifetime by the temperature / humidity biased(THB) test.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.3
• /
• pp.26-34
• /
• 1999

A new silicon-based IC interconnect transmission line parameter extraction methodology is presented and experimentally examined. Unlike the PCB or MCM interconnects, a dominant energy propagation mode in the silicon-based IC interconnects is not quasi-TEM but slow wave mode(SWM). The transmission line parameters are extracted taking the silicon substrate effect (i.e., slow wave mode) into account. The capacitances are calculated considering silicon substrate surface as a ground. Whereas the inductances are calculated by using an effective dielectric constant. In order to verify the proposed method, test patterns were designed. Experimental data have agreement within 10%. Further, crosstalk noise simulation shows excellent agreements with the measurements which are performed with high-speed time domain measurement ( i.e., TDR/TDT measurements) for test pattern, while RC model or RLC model without silicon substrate effect show about 20~25% underestimation error.

• Journal of the Microelectronics and Packaging Society
• /
• v.10 no.3
• /
• pp.89-98
• /
• 2003

The electrical and mechanical properties of sputtered Cu(Mg) films are investigated for highly reliable interconnects. The roughness, adhesion, hardness and resistance to thermal stress of Cu(Mg) film annealed in vacuum at $400^{\circ}C$ for 30min were improved than those of pure Cu film. Moreover, the flat band voltage(V$_{F}$ ) shift in the Capacitance-Voltage(C-V) curve upon bias temperature stressing(BTS) was not observed and leakage currents of Cu(Mg) into $SiO_2$ were three times less than those of pure Cu. Because Mg was easy to react with oxide than Cu and Si after annealing, the Mg Oxide which formed at surface and interface served as a passivation layer as well.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.4
• /
• pp.73-79
• /
• 2007

In this paper the proposed transactor is customized and a generator which roles of automatically generating the transactor according to DUT(Design Under Test)'s input and output is implemented. The customized transactor is designed by rearranging the signals of depending on DUT and transactor protocol which consists of signals of the PCI interface between host computer and FPGA(Field Programmable Gate Array). The implemented automatic generator of transactor generates a Verilog code of transactor by adding DUT's information about input and output ports. Performance and normal working of the generated transactor has been verified by experiments with some verified hardware IPs. Also, an efficiency of the transactor has been verified by comparing with user's manually designed transactor and generated transactor. Moreover, the generator's flexibility has been verified for DUT's information of variable input and output. In case of using the implemented generator, a design time of transactor is reduced.

• Journal of Advanced Navigation Technology
• /
• v.19 no.4
• /
• pp.288-298
• /
• 2015

For the commercialization of unmanned aircraft, we must validate the safety of the air/ground collision alert systems (CAS). The validation procedure of CAS requires the flight test which is not only expensive but also dangerous. To alleviate this problem, we need the simulation based validation process for the CAS. We developed an integrated UAV simulation (IUS) environment which interconnect the flight simulator, the Matlab/Simulink, and a target avionics simulation model. We developed the collision warning module of the TCAS and tested using IUS and flight encounter models. Using IUS, we can evaluate the performance and reliability of a target avionic system at the preliminary design stage of a development life cycle.

• Journal of the Microelectronics and Packaging Society
• /
• v.24 no.2
• /
• pp.69-74
• /
• 2017

Effect of post-annealing treatment times at $200^{\circ}C$ on the peel strength of screen-printed Ag film/polyimide substrate were systematically investigated by $180^{\circ}$ peel test for thermal reliability assessment of printed interconnect. Initial peel strength around 16.7 gf/mm increased up to 29.4 gf/mm after annealing for 24hours, and then sharply decreased to 22.3, 3.6, 0.6, and 0.1 gf/mm after 48, 100, 250, and 500 hours, respectively. Ag-O-C chemical bonding as well as binder organic bridges formations seemed to be responsible for interfacial adhesion improvement after the initial annealing treatment, while excessive Cu oxide formation at Cu/Ag interface seems to be closely related to sharp decrease in peel strength for longer annealing times.