• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.6
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• pp.533-544
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• 1991

In this paper, the performance of bridges used to interconnect LAN to FD야 backbone networks as well as the performance of MAC protocols for FD야 backbone networks were thoroughly analyzed, The exhaustive service discipline and three ource models were applied to analyze the mean waiting time of the system. the performance is evaluated in terms of the service rate of bridge, total load of backbone. medium length of back bone, value of T and station latency. The result of analysis show that in general , processing delay of the system is mainly determined by bridge delays. But when processing time of bridge mereases, processing delays of the system are primarily determined by MAC protocols. Therefore, speed-up of processing time of bridge is necessary to efficiently use the high speed backbone networks.

• ETRI Journal
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• v.33 no.5
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• pp.822-825
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• 2011

Level-encoded dual-rail (LEDR) has been widely used in onchip asynchronous interconnects supporting a 2-phase handshake protocol. However, it inevitably requires 2N wires for N-bit data transfers. Encoder and decoder circuits that perform an asynchronous 2-phase handshake protocol with only N wires for N-bit data transfers are presented for on-chip global interconnects. Their fundamentals are based on a ternary encoding scheme using current-mode multiple valued logics. Using 0.25 ${\mu}m$ CMOS technologies, the maximum reduction ratio of the proposed circuits, compared with LEDR in terms of power-delay product, was measured as 39.5% at a wire length of 10 mm and data rate of 100 MHz.

• ETRI Journal
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• v.36 no.4
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• pp.643-653
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• 2014

To reduce interconnect delay and power consumption while improving chip performance, a three-dimensional integrated circuit (3D IC) has been developed with die-stacking and through-silicon via (TSV) techniques. The power supply problem is one of the essential challenges in 3D IC design because IR-drop caused by insufficient supply voltage in a 3D chip reduces the chip performance. In particular, power bumps and TSVs are placed to minimize IR-drop in a 3D power delivery network. In this paper, we propose a design methodology for 3D power delivery networks to minimize the number of power bumps and TSVs with optimum mesh structure and distribute voltage variation more uniformly by shifting the locations of power bumps and TSVs while satisfying IR-drop constraint. Simulation results show that our method can reduce the voltage variation by 29.7% on average while reducing the number of power bumps and TSVs by 76.2% and 15.4%, respectively.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.3 s.96
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• pp.116-127
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• 1999

Networking for manufacturing is gaining importance as a nerve system of computer-integrated manufacturing (CIM). Among the various network types, the most inexpensive type called fieldbus is specifically aimed to interconnect simple devices such as sensors and actuators. For this purpose, there are several choices of the protocols such as Profibus. WorldFIP, Foundation Fieldbus, and IEC/ISA fieldbus. This paper presents the simulation results of Profibus and WorldFIP. Both protocols have been simulated in order to evaluate the performance such as transmission delay and throughput under different protocol parameter settings and traffic conditions.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.10
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• pp.57-66
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• 2010

Today the various types of communication and application service are provided by the development of Internet and IP technologies. It is expected to be extended the service domain of two networks through the interconnecting P2PSIP overlay which is highlighted as an important technologies for Internet based services and IMS(IP Multimedia Subsystem) which is the new architecture adopted in the evolution of NGN. Therefore, this paper explains the possible methods of the service expansion with interconnecting P2PSIP overlay and IMS network. Specially this paper suggests the interconnection architectures of P2PSIP overlay and IMS network as subscriber's types and analyzes the traffic analysis model and session set up delay characteristics by simulation model. As a results, this paper shows that the interconnection architecture using gateway AS(Application Server) is the excellent method to interconnect the IMS in case of P2PSIP overlay only subscriber, and that interconnection architecture using I-CSCF is good method to interconnect the IMS in case of P2PSIP overlay and IMS subscriber.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.140-140
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• 2018

The 3D interconnect technologies have been appeared, as the density of Integrated Circuit (IC) devices increases. Through Silicon Via (TSV) process is an important technology in the 3D interconnect technologies. And the process is used to form a vertically electrical connection through silicon dies. This TSV process has some advantages that short length of interconnection, high interconnection density, low electrical resistance, and low power consumption. Because of these advantages, TSVs could improve the device performance higher. The fabrication process of TSV has several steps such as TSV etching, insulator deposition, seed layer deposition, metallization, planarization, and assembly. Among them, TSV metallization (i.e. TSV filling) was core process in the fabrication process of TSV because TSV metallization determines the performance and reliability of the TSV interconnect. TSVs were commonly filled with metals by using the simple electrochemical deposition method. However, since the aspect ratio of TSVs was become a higher, it was easy to occur voids and copper filling of TSVs became more difficult. Using some additives like an accelerator, suppressor and leveler for the void-free filling of TSVs, deposition rate of bottom could be fast whereas deposition of side walls could be inhibited. The suppressor was adsorbed surface of via easily because of its higher molecular weight than the accelerator. However, for high aspect ratio TSV fillers, the growth of the top of via can be accelerated because the suppressor is replaced by an accelerator. The substitution of the accelerator and the suppressor caused the side wall growth and defect generation. The suppressor was used as Single additive electrodeposition of TSV to overcome the constraints. At the electrochemical deposition of high aspect ratio of TSVs, the suppressor as single additive could effectively suppress the growth of the top surface and the void-free bottom-up filling became possible. Generally, copper was used to fill TSVs since its low resistivity could reduce the RC delay of the interconnection. However, because of the large Coefficients of Thermal Expansion (CTE) mismatch between silicon and copper, stress was induced to the silicon around the TSVs at the annealing process. The Keep Out Zone (KOZ), the stressed area in the silicon, could affect carrier mobility and could cause degradation of the device performance. Cobalt can be used as an alternative material because the CTE of cobalt was lower than that of copper. Therefore, using cobalt could reduce KOZ and improve device performance. In this study, high-aspect ratio TSVs were filled with cobalt using the electrochemical deposition. And the filling performance was enhanced by using the suppressor as single additive. Electrochemical analysis explains the effect of suppressor in the cobalt filling bath and the effect of filling behavior at condition such as current type was investigated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.7
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• pp.30-36
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• 2010

Due to the scaling of process parameters, the density on chips has been increasing. This trend increases not only the temperature on chips but also the gradient of the temperature depending on distances. In this paper, we propose the balanced skew tree generation technique for minimizing the clock skew that is affected by the temperature gradients on chips. We calculate the interconnect delay using Elmore delay equation, and find out the optimal balanced clock tree by modifying the clock trees that are generated through the DME(Deferred Merge Embedding) algorithm. We have implemented the proposed technique using C language for the performance evaluation. The experimental results show that the clock insertion point generated by the temperature gradient can be lowered below 54% and we confirm that the skew is remarkably decreased after applying the proposed technique.

• Korean Chemical Engineering Research
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• v.47 no.1
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• pp.1-10
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• 2009

As a demand for the portable device requiring smaller size and better performance is in hike, reducing the size of conventionally used planar 2 dimensional chip cannot be a solution for the enhancement of the semiconductor chip technology due to an increase in RC delay among interconnects. To address this problem, a new technology - "3 dimensional (3D) IC chip stack" - has been emerging. For the integration of the technology, several new key unit processes (e.g., silicon through via, wafer thinning and wafer alignment and bonding) should be developed and much effort is being made to achieve the goal. As a result of such efforts, 4 and 8 chip-stacked DRAM and NAND structures and a system stacking CPU and memory chips vertically were successfully developed. In this article, basic theory, configurations and key unit processes for the 3D IC chip integration, and a current tendency of the technology are explained. Future opportunities and directions are also discussed.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.6
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• pp.49-57
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• 2010

In the near future IPTV services will be emerged the various types through Internet, but IMS based IPTV service is one of the very attractive IPTV services. This paper describes the interconnecting architectures of Web based IPTV contents provider to IMS(IP Multimedia System) network and describes the three difference architectures as method to find its IP address. One is the architecture using DNS or HSS to find IP address of Web based IPTV contents provider and connecting gateway function to I-CSCF in IMS. The other is the architecture connecting gateway AS to ISC interface of S-CSCF in IMS. This paper describes the characteristics of traffic generating due to interconnect the Web contents provider, and the traffic model of each architectures. The proposed each architecture is emulated the session establishment delay characteristics in CoD service of IPTV by the simulation. This paper shows that the architecture connecting gateway AS to ISC interface of S-CSCF is the excellent method compare to other two methods in view of the session establishment delay.

• Journal of the Institute of Convergence Signal Processing
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• v.24 no.2
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• pp.112-118
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• 2023

Internet of Things(IoT) technology is developing to a stage where the Internet and objects are connected and objects themselves analyze and judge data to interconnect the real world and the virtual world in real time. This technology consists of sensors, actuators, devices, and networks, and it is being applied in various fields. As the number of IoT devices and applications increases, data traffic also increases. In this paper, a messaging system is designed and implemented in order to analyze the performance between an IoT device and MQTT broker. The experimental was performed to measure MQTT-based round-trip time and message transmission time between the IoT device and the broker. The result shows that there is no packet loss, and propagation delay affects round-trip time.