• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.83-91
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• 2000

This paper presents a new technique to reduce a large interconnect circuit with tens of thousands of elements into the one that is small enough to be analyzed by circuit simulators such as SPICE. This technique takes a fundamentally different approach form the conventional methods based on the interconnect circuit structure analysis and several rules based on the Elmore time constant. The time moments are computed form the circuit consisting of the interconnect circuit and the CMOS gate driver model computed by the AWE technique. Then, the equivalent RC circuit is synthesized from those moments. The characteristics of the driving CMOS gate can be reflected with the high degree of accuracy and the size of the compressed circuit is determined by the number of output nodes regardless of the size of the original interconnect circuits. This technique has been implemented in C language, applied to several interconnect circuits driven by a 0.5${\mu}m$ CMOS gate and the equivalent RC circuits with more than 99% reduction ratio and accuracy with 1 ~ 10% error in therms of propagation delays were obtained.

• 한국전기화학회:학술대회논문집
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• 2001.06a
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• pp.255-258
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• 2001

• Journal of the Microelectronics and Packaging Society
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• v.6 no.4
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• pp.1-7
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• 1999

We developed Fabrication process of embedded passive components in MCM-D substrate. The proposed MCM-D substrate is based on Cu/photosensitive BCB multilayer. The substrate used is Si wafer and Ti/cu metallization is used to form the interconnect layer. Interconnect layers are formed with 1000$\AA$ Ti/3000$\AA$ Cu by sputtering method and 3$\mu\textrm{m}$ Cu by electrical plating method. In order to form the vias in photosensitive BCB layer, the process of BCB and plasma etch using $C_2F_6$ gas were evaluated. The MCM-D substrate is composed of 5 dielectric layers and 4 interconnect layers. Embedded resistors are made with NiCr and implemented on the $2^{nd}$ dielectric layer. The sheet resistance of NiCr is controlled to be about 21 $\Omega$/sq at the thickness of 600$\AA$. The multi-turn sprial inductors are designed in coplanar fashion on the $4^{th}$ interconnect layer with an underpass from the center to outside using the lower $3^{rd}$ interconnect layer. Capacitors are designed and realized between $1^{st}$ interconnect layer and $2^{nd}$ interconnect layer. An important issue in capacitor is the accurate determination of the dielectric thickness. We use the 900$\AA$ thickness of PECVD silicon nitride film as dielectric. Capacitance per unit area is about 88nF/$\textrm {cm}^2$at the thickness of 900$\AA$. The advantage of this integration process is the compatibility with the conventional semiconductor process due to low temperature PECVD silicon nitride process and thermal evaporation NiCr process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.2
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• pp.67-75
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• 2004

This paper presents a buffer insertion method for RLC-class interconnect structured as a sin91e line or a tree. First, a closed form expression for the interconnect delay of a CMOS buffer driving single RLC line is represented. This expression has been derived by the n-th power law for deep submicrometer technology and occurs to be within 9 percentage of maximal relative error in accuracy compared with the results of HSPICE simulation for various RLC loads. This paper proposes a closed form expression based on this for the buffer insertion of single RLC lines and the buffer sizing algorithms for RLC tree interconnects to optimize path delays. The proposed buffer insertion algorithms are applied to insert buffers for several interconnect trees with a 0.25${\mu}{\textrm}{m}$ CMOS technology and the results are compared against those of HSPICE.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.1-8
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• 2000

In this paper, the dependence of interconnect line-induced delay time on the size of CMOSFET gate width is characterized. In case of capacitance dominant interconnect line, the total delay time decreases as transistor size increases. However, there exists a transistor size for minimum total delay time when both of resistance and capacitance of interconnect line become larger than those of transistor. The optimum transistor size for minimum total delay time is obtained using an analytic equation and the experimental results showed good agreement with the calculation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.101-112
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• 2004

In this paper, we developed a numerical analysis model by using ADI-FDTD method to analyze three-dimensional interconnect structure. We discretized maxwell's curl equation by using ADI-FDTD. Using ADI-FDTD method, a sampler circuit designed from 3.3 V CMOS technology is simplified to 3-metal line structure. Using this simplified structure, the time delay and signal distortion of complex interconnects are investigated. As results of simulation, 5∼10 ps of delay time and 0.1∼0.2 V of signal distortion are measured. As demonstrated in this paper, the full-wave analysis using ADI-FDTD exhibits a promise for accurate modeling of electromagnetic phenomena in high-speed VLSI interconnect.

• Korean Journal of Crystallography
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• v.12 no.4
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• pp.233-238
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• 2001

X-ray microdiffraction which uses x-ray beam focused down to a micron size from synchrotron radiation sources allow precision measurements of local orientation and strain variations in polycrystalline materials. Using x-ray microdiffraction setup at Pohang Light Source, we investigated the tex-ture of Cu interconnects with various widths on Si wafer by collecting Laue images and focused to about 2×3㎛ ² in size. Our results show that 1㎛ wide Cu interconnect had grains in rather ran- dom orientation. On the other hand the 20㎛ wide interconnects showed a 〈111〉fiber texture near the center. The grains were 2∼5㎛ long at the 1㎛ wide interconnect and 6∼8㎛ in size at the 20㎛ wide interconnect.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.3
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• pp.1-6
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• 2014

The demand for fine-pitch devices is increasing due to an increase in I/O pin count, a reduction in power consumption, and a miniaturization of chip and package. In addition non-scalability of Cu pillar/Sn cap or Pb-free solder structure for fine-pitch interconnection leads to the development of bumpless interconnection system. Few bumpless interconnect systems such as BBUL technology, SAB technology, SAM technology, Cu-toCu thermocompression technology, and WOW's bumpless technology using an adhesive have been reviewed in this paper: The key requirements for Cu bumpless technology are the planarization, contamination-free surface, and surface activation.

• Journal of the Korean Ceramic Society
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• v.52 no.5
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• pp.344-349
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• 2015

An interconnect is the key component of solid oxide fuel cells that electrically connects unit cells and separates fuel from oxidant in the adjoining cells. To improve their surface stability in high-temperature oxidizing environments, metallic interconnects are usually coated with conductive oxides. In this study, lanthanum nickelates ($LaNiO_3$) with a perovskite structure are synthesized and applied as protective coatings on a metallic interconnect (Crofer 22 APU). The partial substitution of Co, Cu, and Fe for Ni improves electrical conductivity as well as thermal expansion match with the Crofer interconnect. The protective perovskite layers are fabricated on the interconnects by a slurry coating process combined with optimized heat-treatment. The perovskite-coated interconnects show area-specific resistances as low as $16.5-37.5m{\Omega}{\cdot}cm^2$ at $800^{\circ}C$.

• Journal of Navigation and Port Research
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• v.29 no.10 s.106
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• pp.871-876
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• 2005

Application of semiconductor sensors has been widely spreaded into various industries because those have several merits like easy miniaturization and batch production comparison with previous mechanical sensors. But external conditions such as thermal and repetitive load have a bad effect on sensors's lifetime. Especially, this paper was focused on fatigue life of a interconnect made by various materials. Firstly we implemented the stress analysis for interconnect under thermal load and wording pressure. And the fatigue lifetime of each material was induced by Manson & Coffin Equation using the plastic stress-strain curve obtained by the plastic-elastic Finite Element Analysis. The Fatigue lifetime in its bottom is smaller than others and bending load have not an effect on the fatigue lifetime of the interconnect but the stress distribution.