• Advances in materials Research
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• 제1권2호
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• pp.109-113
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• 2012

Electromigration-induced void evolutions in typical upper and lower layer dual-inlaid Copper (Cu) interconnect structures were simulated by applying a phenomenological model resorting to Monte Carlo based simulations, which considers redistribution of heterogeneously nucleated voids and/or pre-existing vacancy clusters at the Copper/dielectric cap interface during electromigration. The results indicate that this model can qualitatively explain the electromigration-induced void evolutions observations in many studies reported by several researchers heretofore. These findings warrant need to re-investigate technologically important electromigration mechanisms by developing rigorous models based on similar concepts.

• ETRI Journal
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• 제30권3호
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• pp.403-411
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• 2008

This paper introduces an interconnect delay fault test (IDFT) controller on boards and system-on-chips (SoCs) with IEEE 1149.1 and IEEE 1500 wrappers. By capturing the transition signals launched during one system clock, interconnect delay faults operated by different system clocks can be simultaneously tested with our technique. The proposed IDFT technique does not require any modification on boundary scan cells. Instead, a small number of logic gates needs to be plugged around the test access port controller. The IDFT controller is compatible with the IEEE 1149.1 and IEEE 1500 standards. The superiority of our approach is verified by implementation of the controller with benchmark SoCs with IEEE 1500 wrapped cores.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권3호
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• pp.370-376
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• 2012

In this work, design considerations for high-performance silicon photodetector are thoroughly investi- gated. Besides the critical dimensions of device, guidelines for process architecture are suggested. Abiding by those criteria for improving both direct-current (DC) and alternating-current (AC) perfor- mances, a high-speed low-operation power silicon photodetector based on p-i-n structure for optical interconnect has been designed by device simulation. An $f_{-3dB}$ of 80 GHz at an operating voltage of 1 V was obtained.

• 전기학회논문지
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• 제60권8호
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• pp.1547-1554
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• 2011

As process parameters scale, interconnect width are reduced rapidly while the current flowing through interconnects does not decrease in a proportional manner. This effect increases current density in metal interconnects which may result in poor reliability. Since RMS(root-mean-square) current limits are used to evaluate self-heating and short-time stress failures caused by high-current pluses, RMS current estimation is very important to guarantee the reliability of semiconductor systems. Hence, it is critical to estimate the current limits through interconnects earlier in semiconductor design stages. The purpose of this paper is to propose a fast, yet accurate RMS current estimation technique that can offer a relatively precise estimate by using closed-form equations. The efficiency and accuracy of the proposed method have been verified through simulations using HSPICE for a vast range of interconnect parameters.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2004년도 국제표면실장 및 인쇄회로기판 생산기자재전:전자패키지기술세미나
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• pp.37-59
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• 2004

In the case of Ni/Au finished pad on the package side, the solder joint of SnAgCu system can bring brittle fracture under impact load such as drop test. Therefore, it's difficult to prevent the brittle fracture of lead-free solder, by controlling Cu content. The failure locus existing on the interface between $(Ni,Cu)_3Sn_4\;and\;(Cu,Ni)_6Sn_5$ IMC layers must be changed to other site in order to avoid brittle fracture due to impact load. It was not found any clear evidence that there were two IMC layers exist. But it was strongly assumed these were two layers which have different Cu-Ni composition. From the above analysis it was assumed that Cu atom in the solder alloy or substrate seemed to affect IMC composition and cause to IMC brittle fracture.

• 대한전자공학회논문지SD
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• 제41권11호
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• pp.53-59
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• 2004

본 논문은 3차원 연결선 모형을 이용하여 효율적으로 회로 연결선에 기생하는 커패시턴스 성분을 추출하는 방법을 제안한다. 제안한 방법은 경험식에 의한 방법 중 2차원 연결선 모형의 커패시턴스를 추출하는 알고리즘을 이용하여 수행시간을 개선하였고, 정확도의 오차를 줄이기 위하여 3차원 커패시턴스 추출에서 이용되는 모형화 방법을 적용하였다. 이 방법은 FastCap을 이용하여 실험한 결과와 비교하면 1.8%의 오차 범위에서 952배의 시간 이득을 얻을 수 있다. 제안한 방법은 VLSI 시스템의 칩 내 외부 연결선의 전기적 변수 추출에 효과적으로 이용될 수 있을 것이다.

• 대한전자공학회논문지SD
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• 제41권11호
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• pp.69-77
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• 2004

본 논문에서는 ground bounce 영향과 지연고장 검출을 함께 고려한 효율적인 보드레벨 연결선 테스트 생성 알고리즘을 제안한다. 제안된 알고리즘은 IEEE 1149.1의 연결선 테스트, ground bounce 영향에 의한 바운더리 스캔의 오동작 방지, 그리고 연결선의 지연고장 검출 능력을 포함한다. 본 논문에서 제안하는 기법은 기존의 기법에 비해 연결선의 지연고장 검출능력을 새롭게 추가하였지만, 연결선 테스트에 필요한 총 테스트 패턴 수는 기존의 기법과 비교해서 큰 차이를 보이지 않음을 실험결과에서 확인할 수 있다.

• 한국전기전자재료학회논문지
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• 제17권12호
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• pp.1289-1295
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• 2004

In this paper, degradation in field-aged PV modules including degradation of interconnect, discoloration of encapsulant and hot spot have been observed and analyzed. From the results, photovoltaic module installed for 6 years shows around 16 % drop of electrical properties due to the interconnect degradation and PV module passed 18 years has been found to drop of around 20 % mainly by the encapsulant discoloration. Furthermore the difference between low and high temperature of PV array at hot spot goes up to 3$0^{\circ}C$ and it leads to interconnect degradation. On the other hands, the temperature difference was observed to be around 15$^{\circ}C$ at the encapsulant discoloration spot of PV array.

• 전기전자학회논문지
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• 제22권2호
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• pp.518-521
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• 2018

차량 내부의 다양한 전자장치를 연결하는 차량 내 통신(IVN: in-vehicle network)은 실시간성, 저잡음성, 고신뢰성, 고유연성 등이 필요하며 CAN(controller area network), CAN-FD(CAN flexible data rate), FlexRay, LIN(local interconnect network), SENT(single edge nibble transmission), PSI5(peripheral sensor interface 5) 등 다양한 기술이 있다. 본 논문에서는 이들 기술의 동작 원리에 대해 살펴보고 각 기술의 적용 대상과 장단점에 대해 설명한다.

• 전자공학회논문지C
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• 제35C권7호
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• pp.20-29
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• 1998

As the packing density of ICs in recent submicron IC design increases, interconnects gain importance. Because interconnects directly affect on two major components of circuit performance, power dissipation and operating speed, circuit engineers are concerned with the optimal design of interconnects and the aid tool to design them. When circuit models of interconnects are given (including geometry and material information), the analysis process for the given structure is not an easy task, but conversely, it is much more difficult to design an interconnect structure with given circuit characteristics. This paper focuses on the latter process that has not been foucsed on much till now due to the complexity of the problem, and prsents a design aid tool(DATOIS) to synthesize interconnects. this tool stroes the circuit performance parameters for normalized interconnect geometries, and has two oeprational modes:analysis mode and synthesis mode. In the analysis mode, circuit performance parameters are obtained by searching the internal database for a given geometry and interpolates results if necessary . In thesynthesis mode, when a given circuit performance parameter satisfies a set of geometry condition in the database, those geometry structures are printed out.