• Transactions on Electrical and Electronic Materials
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• v.3 no.3
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• pp.14-17
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• 2002

The HDP (High Density Plasma) CVD process consists of a simultaneous sputter etch and chemical vapor deposition. As CMOS process continues to scale down to sub- quarter micron technology, HDP process has been widely used fur the gap-fill of small geometry metal spacing in inter-metal dielectric process. However, HBP CVD system has some potential problems including plasma-induced damage. Plasma-induced gate oxide damage has been an increasingly important issue for integrated circuit process technology. In this paper, thin gate oxide charge damage caused by HDP deposition of inter-metal dielectric was studied. Multiple step HDP deposition process was demonstrated in this work to prevent plasma-induced damage by introducing an in-situ top SiH$_4$ unbiased liner deposition before conventional deposition.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.81-81
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• 2007

Chemical mechanical polishing (CMP) 공정은 deep 서브마이크론 집적회로의 다층배선구조률 실현하기 위해 inter-metal dielectric (IMD), inter-layer dielectric layers (ILD), pre-metal dielectric (PMD) 층과 같은 절연막 외에도 W, Al, Cu와 같은 금속층을 평탄화 하는데 효과적으로 사용되고 있으며, 다양한 소자 제작 및 새로운 물질 등에도 광범위하게 응용되고 있다. 하지만 Cu damascene 구조 제작으로 인한 CMP 응용 과정에서, 기계적으로 깨지기 쉬운 65 nm의 소자 이하의 구조에서 새로운 저유전상수인 low-k 물질의 도입으로 인해 낮은 하력의 기계적 연마가 필요하게 되었다. 본 논문에서는 전기화학적 기계적 연마 적용을 위해, I-V 특성 곡선을 이용하여 active, passive, transient, trans-passive 영역의 전기화학적 특성을 알아보았으며, Cu 막의 표면 형상을 알아보기 위해 scanning electron microscopy (SEM) 측정과 energy dispersive spectroscopy (EDS) 분석을 통해 금속 화학적 조성을 조사하였다.

• Transactions on Electrical and Electronic Materials
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• v.3 no.4
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• pp.1-4
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• 2002

As the application of semiconductor chips into electronics increases, it requires more complete integration, which results in higher performance. And it needs minimization in device design for cost saving of manufacture. Therefore oxide gap fill has become one of the major issues in sub-micron devices. Currently HDP (High-Density Plasma) CVD system is widely used in IMD (Inter Metal Dielectric) to fill narrower space between metal lines. However, HDP-CVD system has some potential problems such as plasma charging damage, metal damage and etc. Therefore, we will introduce about one of via resistance failure by metal damage and a preventive method in this paper.

• Korean Journal of Materials Research
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• v.26 no.8
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• pp.427-429
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• 2016

A multi-step deposition process for the gap-filling of submicrometer trenches using dimethyldimethoxysilane (DMDMOS), $(CH_3)_2Si(OCH_3)_2$, and $C_xH_yO_z$ by plasma enhanced chemical vapor deposition (PECVD) is presented. The multi-step process consisted of pre-treatment, deposition, and post-treatment in each deposition step. We obtained low-k films with superior gap-filling properties on the trench patterns without voids or delamination. The newly developed technique for the gap-filling of submicrometer features will have a great impact on inter metal dielectric (IMD) and shallow trench isolation (STI) processes for the next generation of microelectronic devices. Moreover, this bottom up gap-fill mode is expected to be universally for other chemical vapor deposition systems.

• Transactions on Electrical and Electronic Materials
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• v.12 no.4
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• pp.131-134
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• 2011

Back-end-of-line using ultra low-k (ULK; k < 2.5) has been required to reduce resistive capacitance beyond 45 nmtechnologies, because micro-processing units need higher speed and density. There are two strategies to manufacture ULK inter-layer dielectric (ILD) materials using an air-gap (k = 1). The former ULK and calcinations of ILD degrade the mechanical strength and induce a high cost due to the complication of following process, such as chemical mechanical polishing and deposition of the barrier metal. In contrast, the air-gap based low-k ILD with a relatively higher density has been researched on the trench-type with activity, but it has limited application to high density devices due to its high air-gap into the next metal layer. The height of air-gap into the next metal layer was reduced by changing to the via-typed air-gap, up to about 50% compared to that of the trench-typed air-gap. The controllable ULK was easily fabricated using the via-typed air-gap. It is thought that the via-type air-gap made the better design margin like via-patterning in the area with the dense and narrow lines.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.05b
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• pp.34-37
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• 2001

As the integrated circuit device shrinks to smaller dimensions, chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric (IMD) layer with free-defect. However, as the inter-metal dielectrics (IMD) layer gets thinner, micro-scratches are becoming as major defects. Micro-scratches are generated by agglomerated slurry, solidified and attached slurry in pipe line of slurry supply system. To prevent agglomerated slurry particle from inflow, we installed 0.5${\mu}m$ POU (point of use) filter, which is depth-type filter and has 80% filtering efficiency for the $1.0{\mu}m$ size particle. In this paper, we studied the relationship between defect generation and pad count to understand the exact efficiency of the slurry filtration, and to find out the appropriate pad usage. Our preliminary results showed that it is impossible to prevent defect-causing particles perfectly through the depth-type filter. Thus, we suggest that it is necessary to optimize the flow rate of slurry to overcome depth type filters weak-point, and to install the high spray of de-ionized Water (DIW) with high pressure.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.05b
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• pp.30-33
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• 2001

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectrics, which can apply to employed in integrated circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of free-defects in inter-level dielectrics (ILD). Especially, defects like micro-scratch lead to severe circuit failure, and affects yield. CMP slurries can contain particles exceeding $1{\mu}m$ size, which could cause micro-scratch on the wafer surface. The large particles in these slurries may be caused by particle agglomeration in slurry supply line. To reduce these defects, slurry filtration method has been recommended in oxide CMP. In this work, we have studied the effects of filtration and the defect trend as a function of polished wafer count using various filters in inter-metal dielectric(IMD)-CMP. The filter installation in CMP polisher could reduce defect after IMD-CMP. As a result of micro-scratches formation, it shows that slurry filter plays an important role in determining consumable pad lifetime.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.7
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• pp.557-561
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• 2001

Chemical mechanical polishing (CMP) process has been widely used to planarize dielectric layers, which can be applied to the integraded circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of in the defect-free inter-level dielectrics (ILD). Especially, defects such as micro-scratch lead to severe circuit failure which affect yield. CMP slurries can contain particles exceeding 1㎛ in size, which could cause micro-scratch on the wafer surface. The large particles in these slurries may be caused by particles agglomeration in slurry supply line. To reduce these defects, slurry filtration method has been recommended in oxide CMP. In this work, we have studied the effects of filtration and the defect trend as a function of polished wafer count using various filters in inter-metal dielectrics(IMD)-CMP process. The filter installation in CMP polisher could reduce defects after IMD-CMP process. As a result of micro-scratch formation, it is shown that slurry filter plays an important role in determining consumable pad lifetime. The filter lifetime is dominated by the defects. We have concluded that slurry filter lifetime is fixed by the degree of generating defects.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.5
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• pp.191-195
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• 2002

Chemical mechanical Polishing (CMP) process is widely used for the global planarization of inter-metal dielectric (IMD) layer and inter-layer dielectric (ILD) for deep sub-micron technology. However, as the IMD and ILD layer gets thinner, defects such as micro-scratch lead to severe circuit failure, which affect yield. In this paper, for the improvement of CMP process, deionized water (DIW) pressure, purified $N_2$ ($PN_2$) gas, point of use (POU) slurry filler and high spray bar (HSB) were installed. Our experimental results show that DW pressure and P$N_2$ gas factors were not related with removal rate, but edge hot-spot of patterned wafer had a serious relation. Also, the filter installation in CMP polisher could reduce defects after CMP process, it is shown that slurry filter plays an important role in determining consumable pad lifetime. The filter lifetime is dominated by the defects. However, the slurry filter is impossible to prevent defect-causing particles perfectly. Thus, we suggest that it is necessary to install the high spray bar of de-ionized water (DIW) with high pressure, to overcome the weak-point of slurry filter Finally, we could expect the improvements of throughput, yield and stability in the ULSI fabrication process.

• Proceedings of the KIEE Conference
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• 2004.07c
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• pp.1697-1699
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• 2004

In this investigation, we have studied the diffusion of the $Cu^+$ ion in the Cu/Ta/SiOCH/Si and Cu/Ta/$SiO_2$/Si MIS-C structure. The Cu ions diffusion into the Ta barrier and SiOCH was examined by shift in flatband voltage of capacitance-voltage measurement and leakage current of current-voltage measurement. These evalution indicated that $Cu^+$ ion diffusion rate in Ta/SiOCH is considerably lower then the Ta/$SiO_2$ structure. And diffusion barrier Ta(50[nm]) is useful barrier against $Cu^+$ ion diffusion up to 450$^{\circ}C$.